PC7447AMGH1000LB datasheet(27/44 Pages) ATMEL

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5387B–HIREL–07/05

PC7447A [Preliminary]

Table 9-3.

Processor Bus AC Timing Specifications

(1) (at Recommended Operating Conditions, see Table 6-2 on page

10.)

Symbol(2)

Parameter

All Speed Grades

Unit

Min

Max

AVKH

tDVKH

tIVKH

tMVKH

(8)

Input setup times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS,

EXT_QUAL, PMON_IN, SHD[0:1],

BMODE[0:1], BVSEL

1.8

–

tAXKH

DXKH

tIXKH

tMXKH

(8)

Input hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,

PMON_IN, SHD[0:1]

BMODE[0:1], BVSEL

–

tKHAV

KHDV

tKHOV

Output valid times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],

TS, SHD[0:1], WT

–

KHAX

KHDX

tKHOX

Output hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],

TS, SHD[0:1], WT

0.5

–

tKHOE

(5)

SYSCLK to output enable

0.5

–

tKHOZ

(5)

SYSCLK to output high impedance (all except TS, ARTRY, SHD0,

SHD1)

–3.5

tKHTSPZ

(3)(4)(5)

SYSCLK to TS high impedance after precharge

–

tSYSCLK

KHARP

(3)(5)(6)(7)

Maximum delay to ARTRY/SHD0/SHD1 precharge

–

SYSCLK

KHARPZ

(3)(5)(6)(7)

SYSCLK to ARTRY/SHD0/SHD1 high impedance after precharge

–

SYSCLK

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