PC7447AMGH1000LB datasheet(34/44 Pages) ATMEL

34 / 44 page

5387B–HIREL–07/05

PC7447A [Preliminary]

12. Substrate Capacitors for the PC7447A, 360 HITCE

Figure 12-1 shows the connectivity of the substrate capacitor pads for the PC7447A, 360 HITCE. All capacitors are 100 nF.

Figure 12-1. Substrate Bypass Capacitors for the PC7447A, 360 HITCE

13. System Design Information

This section provides system and thermal design recommendations for successful application of

the PC7447A.

13.1 PLL Configuration

The PC7447A PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) fre-

quency, the PLL configuration signals set the internal CPU and VCO frequency of operation.

The PLL configuration for the PC7447A is shown in Table 13-1 on page 35 for a set of example

frequencies. In this example, shaded cells represent settings that, for a given SYSCLK fre-

quency, result in core and/or VCO frequencies that do not comply with the 1400 MHz column in

Table 9-2 on page 25. When enabled, dynamic frequency switching (DFS) also affects the core

frequency by halving the bus-to-core multiplier; see section ”Dynamic Frequency Switching

(DFS)” on page 17 for more information.

C1-2

C1-1

C2-1

C3-1

C4-1

C5-1

C6-1

C6-2

C5-2

C4-2

C3-2

C2-2

C18-1

C18-2 C17-2 C16-2

C15-2 C14-2

C13-2

C13-1

C14-1

C15-1

C16-1

C17-1

A1 CORNER

GND

VDD

GND

VDD

GND

OVDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

C10

GND

VDD

C11

GND

VDD

C12

GND

VDD

C13

GND

VDD

C14

GND

VDD

C15

GND

VDD

C16

GND

OVDD

C17

GND

VDD

C18

GND

OVDD

C19

GND

OVDD

C20

GND

VDD

C21

GND

OVDD

C22

GND

VDD

C23

GND

OVDD

C24

GND

VDD

Capacitor

Pad Number

-1

-2

PC7447AMGH1000LB Datenblatt(PDF) 34 Page - ATMEL Corporation

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