WM8196

Production Data

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PD Rev 4.3 March 2007

17

=

OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST

=

∗ (DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4

PGA NODE: GAIN ADJUST

The signal is then multiplied by the PGA gain,

=

∗ 208/(283- PGA[7:0]) .............................................. Eqn. 5

ADC BLOCK: ANALOGUE-DIGITAL CONVERSION

The analogue signal is then converted to a 16-bit unsigned number, with input range configured by

PGAFS[1:0].

∗ 65535} + 32767 PGAFS[1:0] = 00 or 01 ...... Eqn. 6

∗ 65535}

PGAFS[1:0] = 11 ...............

Eqn. 7

∗ 65535} + 65535 PGAFS[1:0] = 10 ............... Eqn. 8

OUTPUT INVERT BLOCK: POLARITY ADJUST

The polarity of the digital output may be inverted by control bit INVOP.

(INVOP = 0) ......................

Eqn. 9

(INVOP = 1) ......................

Eqn. 10

OUTPUT FORMATS

The digital data output from the ADC is available to the user in 8 or 4-bit wide multiplexed formats by

setting control bit MUXOP[1:0]. Latency of valid output data with respect to VSMP is programmable

by writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing

Diagrams section.

Figure 15 shows the output data formats for Modes 1 – 2 and 4 – 6. Figure 16 shows the output data

formats for Mode 3. Table 2 summarises the output data obtained for each format.

MCLK

4+4+4+4-BIT

OUTPUT

AB

AB

CD

8+8-BIT

OUTPUT

MCLK

4+4+4+4-BIT

OUTPUT

AB

8+8-BIT

OUTPUT

AB

C D

AB

Figure 15 Output Data Formats

(Modes 1

− 2, 4 − 6)

Figure 16 Output Data Formats

(Mode 3)