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WM8569SEDS/V Datenblatt(PDF) 26 Page - Wolfson Microelectronics plc |
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WM8569SEDS/V Datenblatt(HTML) 26 Page - Wolfson Microelectronics plc |
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26 / 36 page ![]() WM8569 Production Data w PD Rev 4.0 June 2006 26 POWERDOWN MODE AND ADC/DAC DISABLE The ADC and DAC may be powered down individually by setting the ADCPD and DACPD disable bits. Setting ADCPD will disable the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when ADCPD is unset. Setting DACPD will disable the DAC and select a low power mode. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 ADCPD 0 ADC Disable: 0: Active 1: Disable 0001010 Powerdown Control 1 DACPD 0 DAC Disable MASTER POWERDOWN This control bit powers down the references for the whole chip. Therefore for complete powerdown, both the ADC and DACs should be powered down first before setting this bit. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001010 Interface Control 4 PWRDNALL 0 Master Power Down Bit: 0: Not powered down 1: Powered down DAC MASTER MODE SELECT Control bit DACMS selects between audio interface Master and Slave Modes. In Master mode, DACLRC and DACBCLK are outputs and are generated by the WM8569. In Slave mode DACLRC and DACBCLK are inputs to WM8569. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001010 Interface Control 5 DACMS 0 DAC Audio Interface Master/Slave Mode Select: 0: Slave mode 1: Master mode MASTER MODE DACLRC FREQUENCY SELECT In Master mode the WM8569 generates DACLRC and DACBCLK. These clocks are derived from the master clock and the ratio of DACMCLK to DACLRC is set by DACRATE. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001010 Interface Control 8:6 DACRATE [2:0] 010 Master Mode MCLK:LRC Ratio Select: 000: 128fs (DAC only) 001: 192fs (DAC only) 010: 256fs 011: 384fs 100: 512fs 101: 768fs |
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