CC1010-RTR1 datasheet(109/152 Pages) TI

109 / 152 page

CC1010

SWRS047

Page 109 of 152

FREQ_0B (0xCD) - Frequency B, Control Register 0

Bit

Name

R/W

Reset value

Description

7:0

FREQ_B(7:0)

R/W

0x4E

8 LSB of frequency control word B.

FSEP1 (0xEB) - Frequency Separation Control Register 1

Bit

Name

R/W

Reset value

Description

7:3

Reserved, read as 0

2:0

FSEP(10:8)

R/W

0x00

3 MSB of the frequency separation control word

FSEP

FSEP0 (0xEA) - Frequency Separation Control Register 0

Bit

Name

R/W

Reset value

Description

7:0

FSEP(7:0)

R/W

0x59

8 LSB of the frequency separation control word

FSEP

PLL (0xE3) - PLL Control Register

Bit

Name

R/W

Reset value

Description

7:3

REFDIV(4:0)

R/W

0x02

Reference divider setting. The main crystal oscillator

frequency is divided by

REFDIV to create the RF

reference frequency fref. Valid

REFDIV settings are 2

through 24, as described above.

ALARM_

DISABLE

R/W

Disable / Enable the generation of the

ALARM_H and

ALARM_L bits

0 : Alarm function enabled

1 : Alarm function disabled

ALARM_H

None

Status bit for tuning voltage out of range (too close to

VDD)

The PLL should be re-calibrated if this bit is set

ALARM_L

None

Status bit for tuning voltage out of range (too close to

GND)

The PLL should be re-calibrated if this bit is set

CC1010-RTR1 Datenblatt(PDF) 109 Page - Texas Instruments

CC1010-RTR1 Datenblatt(HTML) 109 Page - Texas Instruments

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