AM29LV320ML112REF datasheet(12/59 Pages) AMD

12 / 59 page

Am29LV320MH/L

26517B4 January 31, 2007

D A TA

SH EE T

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1.

Device Bus Operations

Legend: L = Logic Low = V

IL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,

AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A20:A0 in word mode; A20:A-1 in byte mode. Sector addresses are A20:A15 in both modes.

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

3. If WP# = V

IL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as

determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped

from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)

4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins operate in the byte or word configuration. If the

BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ0–DQ15 are active and controlled by

CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

VersatileIO

™ (V

IO) Control

The VersatileIO™ (V

IO) control allows the host system

to set the voltage levels that the device generates and

tolerates on CE# and DQ I/Os to the same voltage

level that is asserted on V

IO. See “Ordering Informa-

tion” on page 9 for V

IO options on this device.

Operation

CE#

OE#

WE#

RESET#

WP#

ACC

Addresses

(Note 2)

DQ0–

DQ7

DQ8–DQ15

BYTE#

= V

BYTE#

= V

Read

AIN

OUT

DQ8–DQ14

= High-Z,

DQ15 = A-1

Write (Program/Erase)

(Note 3)

AIN

(Note 4) (Note 4)

Accelerated Program

(Note 3)

AIN

(Note 4) (Note 4)

Standby

VCC ±

0.3 V

VCC ±

0.3 V

High-Z

Output Disable

High-Z

Reset

High-Z

Sector Group Protect

(Note 2)

SA, A6 =L,

A3=L, A2=L,

A1=H, A0=L

(Note 4)

Sector Group Unprotect

(Note 2)

VID

SA, A6=H,

A3=L, A2=L,

A1=H, A0=L

(Note 4)

Temporary Sector Group

Unprotect

(Note 4) (Note 4)

High-Z

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