COM20022I_06 datasheet(23/82 Pages) SMSC

Teilenummer	COM20022I

Bauteilbeschribung	10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

PDF	82 Pages

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Hersteller	SMSC [SMSC Corporation]

Direct Link	http://www.smsc.com

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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I

Page 23

Revision 02-27-06

DATASHEET

The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration

purposes.

Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing

The timing of the Burst mode DMA data transfer is found in the Timing Diagrams section of this data sheet.

The basic sequence of operation is as follows:

nDACK becomes active (low) upon DREQ becoming active (high) and catching the host bus (AEN=

“1”).

DREQ becomes inactive after TC asserts (when nDACK= “0”). In this case, DREQ doesn't become

active again after nDACK becomes inactive.

nDACK becomes inactive after DREQ= 0 and the present cycle finishes.

The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration

purposes.

Figure 5.6

- Burst Mode DMA Data Transfer Rough Timing

DREQ

nDACK

Read/Write

Signal

DREQ

nDACK

Read/Write

Signal

COM20022I Datenblatt(PDF) 23 Page - SMSC Corporation