AVR32AP datasheet(2/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

Introduction

AVR

®32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensi-

tive embedded applications, with particular emphasis on low power consumption and high code

density. In addition, the instruction set architecture has been tuned to allow for a variety of

microarchitectures, enabling the AVR32 to be implemented as low-, mid- or high-performance

processors.

1.1

The AVR family

The AVR family was launched by Atmel

® in 1996 and has had remarkable success in the 8-and

16-bit flash microcontroller market. AVR32 complements the current AVR microcontrollers.

Through the AVR32 family, the AVR is extended into a new range of higher performance appli-

cations that is currently served by 32- and 64-bit processors

To truly exploit the power of a 32-bit architecture, the new AVR32 architecture is not binary com-

patible with earlier AVR architectures. In order to achieve high code density, the instruction

format is flexible providing both compact instructions with 16 bits length and extended 32-bit

instructions. While the instruction length is only 16 bits for most instructions, powerful 32-bit

instructions are implemented to further increase performance. Compact and extended instruc-

tions can be freely mixed in the instruction stream.

1.2

The AVR32 Microprocessor Architecture

The AVR32 is a new innovative microprocessor architecture. It is a fully synchronous synthesi-

sable RTL design with industry standard interfaces, ensuring easy integration into SoC designs

with legacy intellectual property (IP). Through a quantitative approach, a large set of industry

recognized benchmarks have been compiled and analyzed to achieve the best code density in

its class of microprocessor architectures. In addition to lowering the memory requirements, a

compact code size also contributes to the core’s low power characteristics. The processor sup-

ports byte and half-word data types without penalty in code size and performance.

Memory load and store operations are provided for byte, half-word, word and double word data

with automatic sign- or zero extension of half-word and byte data. The C-compiler is closely

linked to the architecture and is able to exploit code optimization features, both for size and

speed.

In order to reduce code size to a minimum, some instructions have multiple addressing modes.

As an example, instructions with immediates often have a compact format with a smaller imme-

diate, and an extended format with a larger immediate. In this way, the compiler is able to use

the format giving the smallest code size.

Another feature of the instruction set is that frequently used instructions, like add, have a com-

pact format with two operands as well as an extended format with three operands. The larger

format increases performance, allowing an addition and a data move in the same instruction in a

single cycle.

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