TMD3721 datasheet(43/89 Pages) OSRAM

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[v3-00] 2023-May-26

TMD3721 − Register O ver view

STATUS_2 Register (Address 0xA1)

Figure 54:

STATUS_2 Register

Addr: 0xA1

STATUS_2

Bit

Bit Name

Default

Access

Bit Description

VSYNC_LOST

R, SC

This flag indicates that VSYNC is not present.

POWER_ON_

RESET

1R, SC

This flag indicates that power on cycle has happened.

0 - No power on reset happened from last read

1 - Power on reset happened from last read

This flag is clear-by-read by default.

5PWINT

RW, SC

This flag is set when PWTIME is completed if PWIEN =1.

This flag is set only in parallel/concurrent mode and only

when PWEN = 1.

Reserved

RW, SC

Reserved. Must be set to default value.

PSAT_1STG_AMB

RW, SC

This flag indicates proximity saturation is from first stage

of proximity engine due to ambient in subtraction

phase.

PSAT_1STG_

PULSE

0RW, SC

This flag indicates proximity saturation is from first stage

of proximity engine when VCSEL pulse is emitted.

VSYNC_LOST_INT

RW, SC

Interrupt when VSYNC watchdog timeout happens or

internal oscillator is stopped e.g PON=0. This interrupt

generated on event based.

VSYNC_CHG_INT

RW, SC

Interrupt when there is a change in VSYNC period

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