TMD3721 datasheet(44/89 Pages) OSRAM

44 / 89 page

Datasheet, Public

Page 43

[v3-00] 2023-May-26

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TMD3721 − Register Overview

STATUS_3 Register (Address 0xA2)

Figure 55:

STATUS_3 Register

All flags with access type of RW, SC in STATUS, STATUS_2, and

STATUS_3 registers can be cleared by setting the bit high.

Alternatively, if the INT_READ_CLEAR in the CFG3 register bit is

set, then simply reading these registers automatically clears all

flags.

PID_L Register (Address 0xA5)

Figure 56:

PID_L Register

Addr: 0xA2

STATUS_3

Bit

Bit Name

Default

Access

Bit Description

PWM_PRD_CHG_

INT

RW, SC

Interrupt when there is a change in PWM period

6:5

Reserved

RW, SC

Reserved. Must be set to default value.

ATINT

RW, SC

Interrupt when ATIME is completed.

3FTINT

RW, SC

Interrupt when FIFO_LVL crosses FIFO_THR_LVL. FTIEN

needs to be set.

2AWINT

RW, SC

Interrupt when AWTIME is completed. To enable AWINT,

both AWEN and AWIEN have to be set.

ASAT

RW, SC

ALS analog saturation.

0AINT

RW, SC

ALS interrupt flag indicates that ALS results have

exceeded the AILT or AIHT thresholds and persistence

settings.

Addr: 0xA5

PID_L

Bit

Bit Name

Default

Access

Bit Description

7:0

PID_L

0x00

The low byte of the 16bit programmable Proximity ID.

Whenever a proximity pulse is triggered during ASP1

ASP2 sampling period in Full Parallel Mode, PID is

written into the FIFO instead of the actual ALS data if

PID_EN is 1.

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