IA88C00-PDW48I-R datasheet(35/80 Pages) INNOVASIC

35 / 80 page

IA88C00

Data Sheet

Microcontroller

As of Production Version -01

ENG 21 0 050519-00

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D4 - REIE - Receive Error Interrupt Enable - If this bit is set to 1, any receiver error condition will

cause an interrupt request. Possible receive error conditions include parity error, overrun error and

framing error.

D5 - BRKIE - Break Interrupt Enable - If this bit is set to 1, a transition in either direction on the break

signal will cause an interrupt request.

D6 - CCIE - Control Character Interrupt Enable - If this bit is set to 1, an ASCII Control Character

Detect signal in the URC register will cause an interrupt.

D7 - WUIE - Wake-Up Interrupt Enable - If this bit is set to 1, any of the wake-up conditions that set

the Wake-Up Detect bit (WUD) in the URC register will cause an interrupt request.

Figure 32. UART Transmit Interrupt Register, UTI R238 Bank 0

Bit

Initial Value

Read/Write

R/W

R/O

R/W

The timing for the transmit buffer empty interrupt is software programmable. There are two different

interrupt timings selectable with 1 bit.

Option 1: Interrupt is activated at the moment the contents of the TUIO register are transferred to the Tx

FIFO.

Option 2: Interrupt is activated at the moment the last stop bit in the Tx FIFO is sent.

After loading the transmit shift register, UART control generates a buffer empty flag to indicate that

TUIO is ready to be filled with new data.

A new flag will indicate when the transmit shift register is empty.

D0 - If this bit is zero, a high value of D2 in the UIE register will cause an interrupt on Transmit UIO

empty. If this bit is set, a high value of D2 in the UIE register will cause an interrupt on transmit shift

writing to the UIO register.

D1 - This flag is set when the transmit shift register is empty and is reset when a new value is loaded into

the UIO. This flag will not be set during a send break.

Figure 33. Uart Data Register (UIO), R239 Bank 0

Bit

Initial Value

Read/Write

R/W

R/O

R/W

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