TMP112ASLASHBSLASHN datasheet(17/47 Pages) TI1

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7.3.2 Serial Interface

The TMP112 family operates as a slave device only on the SMBus, two-wire, and I2C interface-compatible bus.

Connections to the bus are made through the open-drain I/O lines, SDA and SCL. The SDA and SCL pins

feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus

noise. The TMP112 family supports the transmission protocol for fast (1 kHz to 400 kHz), fast-plus (1 kHz to 1

MHz) and high-speed (1 kHz to 2.85 MHz) modes. All data bytes are transmitted MSB first.

7.3.2.1 Bus Overview

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The

bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions.

To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a high-

to low-logic level when the SCL pin is high. All slaves on the bus shift in the slave address byte on the rising

edge of the clock, with the last bit indicating whether a read or write operation is intended. During the ninth clock

pulse, the slave being addressed responds to the master by generating an acknowledge and pulling the SDA pin

low.

A data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During the data

transfer the SDA pin must remain stable when the SCL pin is high, because any change in the SDA pin when the

SCL pin is high is interpreted as a START or STOP signal.

When all data have been transferred, the master generates a STOP condition indicated by pulling the SDA pin

from low to high when the SCL pin is high.

7.3.2.2 Serial Bus Address

To communicate with the device, the master must first address slave devices through a slave-address byte. The

slave-address byte consists of seven address bits and a direction bit indicating the intent of executing a read or

write operation.

The TMP112 family features an address pin to allow up to four devices to be addressed on a single bus. Table

7-4 describes the pin logic levels used to properly connect up to four devices. This table also describes four

different address options available when ALERT pin is used in TMP112Dx.

Table 7-4. Address and Alert Variant Device Target Address

DEVICE ORDERABLE

ADD0 PIN CONNECTION

DEVICE I2C BUS

ADDRESS

DEVICE I2C BUS

ADDRESS (Hex)

Address Variant Only

TMP112D

GND

1000000

40h

V+

1000001

41h

SDA

1000010

42h

SCL

1000011

43h

Alert Variant Only

TMP112D0

N/A

1001000

48h

TMP112D1

1001001

49h

TMP112D2

1001010

4Ah

TMP112D3

1001011

4Bh

Address + Alert Variant

TMP112A

TMP112B

TMP112N

GND

1001000

48h

V+

1001001

49h

SDA

1001010

4Ah

SCL

1001011

4Bh

7.3.2.3 Writing and Reading Operation

Accessing a particular register on the TMP112 family is accomplished by writing the appropriate value to the

pointer register. The value for the pointer register is the first byte transferred after the slave address byte with the

R/W bit low. Every write operation to the TMP112 family requires a value for the pointer register (see Figure 7-4).

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TMP112

SBOS473J – MARCH 2009 – REVISED FEBRUARY 2024

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