TMP112ASLASHBSLASHN datasheet(26/47 Pages) TI1

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7.5.3.4 Fault Queue (F1/F0)

A fault condition exists when the measured temperature exceeds the user-defined limits set in the THIGH and

TLOW registers. Additionally, the number of fault conditions required to generate an alert, can be programmed

using the fault queue. The fault queue is provided to prevent a false alert as a result of environmental noise. The

fault queue requires consecutive fault measurements to trigger the alert function. Table 7-11 lists the number of

measured faults that can be programmed to trigger an alert condition in the device. For THIGH and TLOW register

format and byte order, see the High- and Low-Limit Registers section.

Table 7-11. TMP112 family Fault Settings

CONSECUTIVE FAULTS

7.5.3.5 Converter Resolution (R1 and R0)

The converter resolution bits, R1 and R0, are read-only bits. The TMP112 family converter resolution is set on

start up to 11 which sets the temperature register to a 12-bit resolution.

7.5.3.6 One-Shot (OS)

When the device is in shutdown mode, writing a 1 to the OS bit begins a single temperature conversion. During

the conversion, the OS bit reads 0. The device returns to the SHUTDOWN state at the completion of the single

conversion. For more information on the one-shot conversion mode, see the Section 7.4.3 section.

7.5.3.7 Extended Mode (EM)

The extended mode bit configures the device for normal mode operation (EM = 0) or extended mode operation

(EM = 1). In normal mode, the temperature register and the high and low limit registers use a 12-bit data format.

For more information on the extended mode, see the Section 7.4.2 section.

7.5.3.8 Alert (AL)

The AL bit is a read-only function. Reading the AL bit provides information about the comparator mode status.

The state of the POL bit inverts the polarity of data returned from the AL bit. When the POL bit equals 0, the AL

bit reads as 1 until the temperature equals or exceeds T(HIGH) for the programmed number of consecutive faults,

causing the AL bit to read as 0. The AL bit continues to read as 0 until the temperature falls below T(LOW) for the

programmed number of consecutive faults, when the device again reads as 1. The status of the TM bit does not

affect the operation of the AL bit.

7.5.4 High- and Low-Limit Register

The temperature limits are stored in the T(LOW) and T(HIGH) registers in the same format as the temperature

result, and the values are compared to the temperature result on every conversion. The outcome of the

comparison drives the behavior of the ALERT pin/flag, which operates as a comparator output or an interrupt,

and is set by the TM bit in the configuration register.

In Comparator mode (TM = 0), the ALERT pin and status flag become active when the temperature equals or

exceeds the value in the T(HIGH) register and generates a consecutive number of faults according to fault bits F1

and F0. The ALERT pin and status flag remain active until the temperature falls below the indicated T(LOW) value

for the same number of faults.

In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds the value

in T(HIGH) for a consecutive number of fault conditions (as shown in Table 7-11). The ALERT pin remains active

until a read operation of any register occurs, or the device successfully responds to the SMBus alert response

address. The ALERT pin is also cleared if the device is placed in shutdown mode. When the ALERT pin

is cleared, the pin becomes active again only when temperature falls below T(LOW), and remains active until

cleared by a read operation of any register or a successful response to the SMBus alert response address.

TMP112

SBOS473J – MARCH 2009 – REVISED FEBRUARY 2024

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