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MPC8540CPX667JC Datenblatt(PDF) 94 Page - Freescale Semiconductor, Inc |
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MPC8540CPX667JC Datenblatt(HTML) 94 Page - Freescale Semiconductor, Inc |
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94 / 104 page ![]() MPC8540 Integrated Processor Hardware Specifications, Rev. 4 94 Freescale Semiconductor System Design Information Figure 53. COP Connector Physical Pinout 17.8.1 Termination of Unused Signals If the JTAG interface and COP header will not be used, Freescale recommends the following connections: •TRST should be tied to HRESET through a 0 k Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in Figure 54. If this is not possible, the isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations. • Tie TCK to OVDD through a 10 kΩ resistor. This will prevent TCK from changing state and reading incorrect data into the device. • No connection is required for TDI, TMS, or TDO. 3 13 9 5 1 6 10 15 11 7 16 12 8 4 KEY No pin 1 2 COP_TDO COP_TDI NC NC COP_TRST COP_VDD_SENSE COP_CHKSTP_IN NC NC GND COP_TCK COP_TMS COP_SRESET COP_HRESET COP_CHKSTP_OUT |
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