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MB95130M Datenblatt(PDF) 20 Page - fujitsu semiconductor |
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MB95130M Datenblatt(HTML) 20 Page - fujitsu semiconductor |
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20 / 63 page ![]() MB95130M Series 20 The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: The DP specifies the area for mapping instructions (16 different types of instructions such as MOV A and dir) using direct addresses to 0080H to 00FFH. The CCR consists of the bits indicating arithmetic operation results or transfer data content and the bits that control CPU operations at interrupt. Direct bank pointer (DP2 to DP0) Specified address area Mapping area XXXB (no effect to mapping) 0000H to 007FH 0000H to 007FH (without mapping) 000B (initial value) 0080H to 00FFH 0080H to 00FFH (without mapping) 001B 0100H to 017FH 010B 0180H to 01FFH 011B 0200H to 027FH 100B 0280H to 02FFH 101B 0300H to 037FH 110B 0380H to 03FFH 111B 0400H to 047FH H flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”. The flag is cleared to “0” when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by these bits. IL1 IL0 Interrupt level Priority 00 0 High Low = no interruption 01 1 10 2 11 3 N flag : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the bit is set to “0”. Z flag : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise. V flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” otherwise. C flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. • Rule for Conversion of Actual Addresses in the General-purpose Register Area Generated address RP upper OP code lower "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1 b0 A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8 |
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