Data Sheet

LT3077

analog.com

Rev. 0

28 of 38

BIAS Undervoltage Lockout

An internal undervoltage lockout (UVLO) comparator monitors the BIAS rail. If VBIAS drops below the UVLO threshold,

all functions shut down, the pass transistors are gated off, and output currents fall to zero. The typical BIAS pin UVLO

threshold is 2.2V on the rising edge of VBIAS. The UVLO circuit incorporates about 130mV of hysteresis on the falling

edge of VBIAS.

Power Good

The PG pin is an open-drain NMOS output that actively pulls low if EN is low or if any one of these fault modes is

detected:



VOUT is less than 93% of VOUT(NOMINAL) on the rising edge of VOUT.



VOUT is less than 90% of VOUT(NOMINAL) on the falling edge of VOUT.



VBIAS is less than its undervoltage lockout threshold.



The OUT-over-IN voltage detector activates.

Stability and Output Capacitance

The LT3077 feedback loop requires a minimum output capacitance of 10μF for stability. ADI recommends mounting

low ESR, X5R, or X7R ceramic capacitors near the LT3077 OUT and GND pins. Include wide routing planes for OUT

and GND to minimize inductance. If possible, mount the regulator immediately adjacent to the application load to

minimize distributed inductance for optimal load transient performance. Point-of-load applications present the

best-case layout scenario for extracting full LT3077 performance.

Additional ceramic capacitors distributed beyond the immediate decoupling capacitors are acceptable and

recommended at the point of the load because the distributed PCB inductance isolates them from the primary

compensation capacitors.

Many of the applications in which the LT3077 excels, such as FPGA, ASIC processor, or DSP supplies, typically require

a high-frequency decoupling capacitor network for the device being powered. This network generally consists of

many low-value ceramic capacitors in parallel. In parallel, multiple low-value capacitors present a favorable

frequency characteristic that reduces the parasitic inductance of the capacitors.

Consider the use of ceramic capacitors. Ceramic capacitors are manufactured with various dielectrics, each with

different temperatures and applied voltage behavior. The most common dielectrics are specified with EIA

temperature characteristic codes of Z5U, Y5V, X5R, and X7R. The Z5U and Y5V dielectrics are suitable for providing

high capacitances in a small package, but they tend to have strong voltage and temperature coefficients, as shown

in Figure 67 and Figure 68. When used with a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an effective value as

low as 1μF to 2μF for the DC bias voltage applied and over the operating temperature range. The X5R and X7R

dielectrics result in more stable characteristics and are more suitable for use as the output capacitor.

The X7R type has better stability across temperatures, while the X5R is less expensive and is available in higher

values. Care still must be exercised when using X5R and X7R capacitors; the X5R and X7R codes only specify the

operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC

bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors but can still be significant enough to drop

capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component case size

increases but expected capacitance at operating voltage should be verified. Voltage and temperature coefficients

are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device

generates a voltage across its terminals due to mechanical stress, similar to how a piezoelectric microphone works.

For a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients.

A N A L O G D E V I C E S

C O N F I D E N T I A L