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LT3077ACRZ-R7 Datenblatt(PDF) 11 Page - Analog Devices

Teilenummer LT3077ACRZ-R7
Bauteilbeschribung  5.5V, 3A, Ultra-Low Noise, High PSRR, 85mV Dropout Ultra-Fast Linear Regulator
PDF  38 Pages
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LT3077ACRZ-R7 Datenblatt(HTML) 11 Page - Analog Devices

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Data Sheet
LT3077
analog.com
Rev. 0
11 of 38
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 5. Pin Descriptions
PIN
NAME
DESCRIPTION
1
EN
Device Enable. EN pin enables/disables the output. The LT3077 typically turns on when
the EN voltage exceeds 1.26V on the rising edge, with an 80mV hysteresis on its falling
edge. Pulling this pin low pulls down the reference, disables the output transistor, and
disables auxiliary functions. Alternatively, the EN pin can set a BIAS-supply UVLO
threshold by using a resistor-divider between BIAS, EN, and GND. If unused, connect
EN to BIAS. Do not float the EN pin.
2, 3, 4
VO0, VO1, VO2
Output Voltage Select. These tri-level pins combine to select a nominal output voltage
from 0.5V to 4.2V. The input logic low threshold is less than 300mV referenced to GND,
and the logic high threshold is greater than 1.97V referenced to GND. The range
between 0.95V and 1.15V defines the logic Hi-Z state. See Table 6 in the Applications
Information section that defines the VOUT versus VO0, VO1, and VO2 settings.
5
PG
Power Good. The PG pin is an open-drain NMOS output that actively pulls low if EN is
low or if any one of these fault modes is detected:
VOUT is less than 93% of VOUT(NOMINAL) on the rising edge of VOUT.
VOUT is less than 90% of VOUT(NOMINAL) on the falling edge of VOUT.
VBIAS is less than its undervoltage lockout threshold.
The OUT-over-IN voltage detector activates.
6, 7
OUT
Output. The exposed pad consisting of pins 6-7 of the LFCSP-RT package is the
electrical connection to OUT. These pins supply power to the load. Connect the entire
OUT exposed pad consisting of pins 6-7 for proper electrical and thermal performance.
A minimum output capacitance of 10µF is required for stability. ADI recommends low
ESR, X5R or X7R dielectric ceramic capacitors for best performance. Large load
transient applications require larger output capacitors to limit peak voltage transients.
1
EN
2
VO0
3
VO1
4
VO2
5
PG
10 GND
11 REF
12 ILIM
13 BIASF
14 BIAS
LT3077
TOP VIEW
(Not to Scale)
LFCSP-RT PACKAGE
18-LEAD (3mm × 3mm × 0.58mm)
TJMAX = 125°C, θJA = 44°C/W
A N A L O G D E V I C E S
C O N F I D E N T I A L



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