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ST7LITE49M Datenblatt(PDF) 81 Page - STMicroelectronics |
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ST7LITE49M Datenblatt(HTML) 81 Page - STMicroelectronics |
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81 / 188 page ![]() ST7LITE49M On-chip peripherals 81/188 Figure 37. Single Timer mode (ENCNTR2=0) Figure 38. Dual Timer mode (ENCNTR2=1) PWM0 PWM1 PWM2 PWM3 Dead Time Generator PWM3 Duty Cycle Generator 12-bit Input Capture PWM2 Duty Cycle Generator PWM1 Duty Cycle Generator PWM0 Duty Cycle Generator 12-Bit Autoreload register 1 12-Bit Upcounter 1 Output Compare CMP Interrupt OVF1 interrupt Edge Detection Circuit OE0 OE1 OE2 OE3 DTE bit BPEN bit ATIC Clock Control fCPU Lite timer 1 ms from OFF PWM0 PWM1 PWM2 PWM3 Dead Time Generator PWM3 Duty Cycle Generator 12-bit Input Capture 12-Bit Autoreload register 2 12-Bit Upcounter 2 PWM2 Duty Cycle Generator PWM1 Duty Cycle Generator PWM0 Duty Cycle Generator 12-Bit Autoreload register 1 12-Bit Upcounter 1 Output Compare CMP Interrupt OVF1 interrupt OVF2 interrupt Edge Detection Circuit OE0 OE1 OE2 OE3 ATIC DTE bit BPEN bit LTIC OP_EN bit Clock Control fCPU One Pulse mode Output Compare CMP Interrupt Lite timer 1 ms from OFF |
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