PS700 datasheet(32/38 Pages) MICROCHIP

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PS700

DS21760F-page 32

 2004 Microchip Technology Inc.

TABLE 6-3:

AC CHARACTERISTICS (TA = -20°C TO +85°C; VDD (INTERNAL) = +3.3V ± 10%)

TABLE 6-4:

AC CHARACTERISTICS – SMBus (TA = -20°C TO +85°C; VDD (INTERNAL) = +3.3V ± 10%)

Note 1:

tHIGH max. provides a simple, ensured method for devices to detect bus Idle conditions.

tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from

the initial start to the stop.

tLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a

message as defined from Start-to-Ack, Ack-to-Ack or Ack-to-Stop.

Rise and fall time is defined as follows: tR = (VILMAX – 0.15) to (VIHMIN + 0.15)

tF = 0.9VDD to (VILMAX – 0.15)

TABLE 6-5:

A/D CONVERTER CHARACTERISTICS (TA = -20°C TO +85°C;

VREG (INTERNAL) = +3.3V ±10%)

Note 1:

Voltage is internal at A/D converter inputs. VSR and VNTC are measured directly. VC(x) inputs are measured

using internal level translation circuitry that scales the input voltage range appropriately for the converter.

Symbol

Description

Min

Typ.

Max

Units

Condition

fRC

Internal RC Oscillator Frequency

130,613

131,072

131,530

fA/D

Internal A/D Operating Clock

—

fRC/4

—

tPOR

Power-on Reset Delay

—

Delay from time when VC1

voltage exceeds 2.7V

tSHELF

Delay to entry of Shelf-Sleep mode

—

(SHent = 1 or VPACK < VPtrip)

and (SDA and SCL go low)

tWAKE

Delay to exit of Shelf-Sleep mode

—

SDA and SCL go high

Symbol

Description

Min

Typ.

Max

Units

Condition

fSMB

SMBus Clock Operating Frequency

—

100

kHz

Slave mode

tBUF

Bus Free Time between Start and Stop

4.7

—

µs

tSHLD

Bus Hold Time after Repeated Start

4.0

—

µs

tSU:STA

Setup Time before Repeated Start

4.7

—

µs

tSU:STOP

Stop Setup Time

4.0

—

µs

tHLD

Data Hold Time

—

tSETUP

Data Setup Time

250

—

tLOW

Clock Low Period

4.7

—

µs

tHIGH

Clock High Period

4.0

—

µs

(Note 1)

tLOW:SEXT

Message Buffering Time

—

(Note 2)

tHIGH:MEXT

Message Buffering Time

—

(Note 3)

Clock/Data Fall Time

—

300

(Note 4)

Clock/Data Rise Time

—

1000

(Note 4)

Symbol

Description

Min

Typ.

Max

Units

Condition

ADRES

A/D Converter Resolution

—

bits

(Note 1)

tCONV

A/D Conversion Measurement Time, n-bit

—

2(n + 1)/fA/D

—s

VADIN

A/D Converter Input Voltage Range (internal)

-152

—

152

VR = 170 mV

—

309

VR = 340 mV

EVGAIN

Supply Voltage Gain Error

—

0.100

EVOFFSET Compensated Offset Error

—

0.100

ETEMP

Temperature Gain Error

—

0.100

EINL

Integrated Nonlinearity Error

—

0.004

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