DS2155_06 datasheet(7/238 Pages) DALLAS

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DS2155

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Figure 35-23. Transmit IBO Frame Interleave Mode Timing ................................................................................. 221

Figure 37-1. Intel Multiplexed Bus Read Timing (BTS = 0/MUX = 1).................................................................. 225

Figure 37-2. Intel Multiplexed Bus Write Timing (BTS = 0/MUX = 1)................................................................. 225

Figure 37-3. Motorola Multiplexed Bus Timing (BTS = 1/MUX = 1) ................................................................... 226

Figure 37-4. Intel Nonmultiplexed Bus Read Timing (BTS = 0/MUX = 0) ........................................................... 228

Figure 37-5. Intel Nonmultiplexed Bus Write Timing (BTS = 0/MUX = 0) .......................................................... 228

Figure 37-6. Motorola Nonmultiplexed Bus Read Timing (BTS = 1/MUX = 0).................................................... 229

Figure 37-7. Motorola Nonmultiplexed Bus Write Timing (BTS = 1/MUX = 0)................................................... 229

Figure 37-8. Receive-Side Timing .......................................................................................................................... 231

Figure 37-9. Receive-Side Timing, Elastic Store Enabled ...................................................................................... 232

Figure 37-10. Receive Line Interface Timing ......................................................................................................... 232

Figure 37-11 Receive Timing Delay RCLK to BPCLK......................................................................................... 233

Figure 37-12. Transmit-Side Timing....................................................................................................................... 235

Figure 37-13. Transmit-Side Timing, Elastic Store Enabled................................................................................... 236

Figure 37-14. Transmit Line Interface Timing........................................................................................................ 236

1.2 Table of Tables

Table 4-A. Pin Description Sorted by Pin Number ................................................................................................... 30

Table 5-A. Register Map Sorted by Address............................................................................................................. 33

Table 9-A. T1 Alarm Criteria .................................................................................................................................... 54

Table 10-A. E1 Sync/Resync Criteria ....................................................................................................................... 56

Table 10-B. E1 Alarm Criteria .................................................................................................................................. 61

Table 14-A. T1 Line Code Violation Counting Options ........................................................................................... 76

Table 14-B. E1 Line-Code Violation Counting Options ........................................................................................... 76

Table 14-C. T1 Path Code Violation Counting Arrangements.................................................................................. 78

Table 14-D. T1 Frames Out-of-Sync Counting Arrangements ................................................................................. 79

Table 16-A. Time Slot Numbering Schemes............................................................................................................. 90

Table 17-A. Idle-Code Array Address Mapping ....................................................................................................... 96

Table 17-B. GRIC and GTIC Functions.................................................................................................................... 98

Table 19-A. Elastic Store Delay After Initialization ............................................................................................... 108

Table 23-A. HDLC Controller Registers................................................................................................................. 127

Table 24-A. Component List (Software-Selected Termination, Metallic Protection)............................................. 156

Table 24-B. Component List (Software-Selected Termination, Longitudinal Protection)...................................... 157

Table 24-C. Transformer Specifications.................................................................................................................. 158

Table 27-A. Transmit Error-Insertion Setup Sequence ........................................................................................... 180

Table 27-B. Error Insertion Examples..................................................................................................................... 182

Table 34-A. Instruction Codes for IEEE 1149.1 Architecture ................................................................................ 203

Table 34-B. ID Code Structure................................................................................................................................ 204

Table 34-C. Device ID Codes.................................................................................................................................. 204

Table 34-D. Boundary Scan Control Bits................................................................................................................ 205

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