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DS2155 Datenblatt(PDF) 21 Page - Dallas Semiconductor

Teilenummer DS2155
Bauteilbeschribung  T1/E1/J1 Single-Chip Transceiver
PDF  238 Pages
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Hersteller  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2155 Datenblatt(HTML) 21 Page - Dallas Semiconductor

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Signal Description:
Transmit Clock Output
Signal Type:
Output
Buffered clock that is used to clock data through the transmit-side formatter (i.e., either TCLK or RCLKI). This pin
is normally connected to TCLKI.
Signal Name:
TPOSI
Signal Description:
Transmit Positive-Data Input
Signal Type:
Input
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected
to TPOSO by connecting the LIUC pin high. TPOSI and TNEGI can be connected together in NRZ applications.
Signal Name:
TNEGI
Signal Description:
Transmit Negative-Data Input
Signal Type:
Input
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected
to TNEGO by connecting the LIUC pin high. TPOSI and TNEGI can be connected together in NRZ applications.
Signal Name:
TCLKI
Signal Description:
Transmit Clock Input
Signal Type:
Input
Line interface transmit clock. Can be internally connected to TCLKO by connecting the LIUC pin high.
4.2 Receive Side
Signal Name:
RLINK
Signal Description:
Receive Link Data
Signal Type:
Output
T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a
frame.
E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK.
Signal Name:
RLCLK
Signal Description:
Receive Link Clock
Signal Type:
Output
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output.
E1 Mode: A 4kHz to 20kHz clock.
Signal Name:
RCLK
Signal Description:
Receive Clock
Signal Type:
Output
1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer.
Signal Name:
RCHCLK
Signal Description:
Receive Channel Clock
Signal Type:
Output
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Synchronous with RCLK
when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is
enabled. Useful for parallel-to-serial conversion of channel data.



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