Data Sheet

ADHV4702-1

ABSOLUTE MAXIMUM RATINGS

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Rev. D | 5 of 22

Table 2.

Parameter

Rating

Supply Voltage

VCC to VEE

225 V

VCC to GND

180 V

VEE to GND

−180 V

Output Voltage

VCC to VEE

Common-Mode Input Voltage

VCC to VEE

Differential Input Voltage

±2.0 V

Input Current

±5 mA

DGND Voltage

VCC − 12 V to VEE

Voltage

RESERVED, SD, and TMP Pins

DGND to DGND + 6 V

COMP Pin

VCC − 5 V to VCC

RADJ Pin

DGND to DGND + 0.6 V

Storage Temperature Range

−65°C to +150°C

Operating Temperature Range

−40°C to +85°C

Lead Temperature (Soldering 10 sec)1

260°C

Junction Temperature (TJ)

150°C

1 See IPC/JEDEC J-STD-020 for more information.

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress

rating only; functional operation of the product at these or any other

conditions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum operat-

ing conditions for extended periods may affect product reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the package is limited

by the associated rise in TJ on the die. At approximately 150°C,

which is the glass transition temperature, the plastic begins to

change its properties. Exceeding a TJ of 150°C can result in

changes in the silicon devices, potentially causing failure. Table 3

shows the junction-to-case thermal resistance (θJC) for the LFCSP.

For more detailed information on power dissipation and thermal

management, see the Applications Information section.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to PCB

thermal design is required.

θJA is the natural convection, junction to ambient thermal resistance

measured in a one cubic foot sealed enclosure. θJC is the junction

to case thermal resistance.

Table 3. Thermal Resistance

Package Type

θJA

θJC

Unit

CP-12-81

37

1

°C/W

1 The data is collected from a 2S2P board. A cold plate is attached to the

bottom side of the PCB using 100 µm thermal interface material (TIM) for θJC

simulation. See JEDEC standard for additional information.

ELECTROSTATIC DISCHARGE (ESD) RATINGS

The following ESD information is provided for handling of ESD-sen-

sitive devices in an ESD protected area only.

Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.

Field induced charged device model (FICDM) and charged device

model (CDM) per ANSI/ESDA/JEDEC JS-002.

Machine model (MM) per ANSI/ESD STM5.2. MM voltage values

are for characterization only.

ESD Ratings for ADHV4702-1

Table 4. ADHV4702-1, 12-Lead LFCSP

ESD Model

Withstand Threshold

(V)

Class

FICDM

±750

C3

HBM

±1000

1C

MM

±100

A

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Charged devi-

ces and circuit boards can discharge without detection. Although

this product features patented or proprietary protection circuitry,

damage may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.