Data Sheet

ADHV4702-1

THEORY OF OPERATION

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Rev. D | 19 of 22

Figure 61. Dynamic SOA at TA = 25°C and TA = 85°C With and Without Input

Clamping Diodes, AV = 20, VS = ±110 V, RF = 100 kΩ, RLOAD = 10 kΩ, RADJ = 0

Ω

Figure 62. DC SOA at TA = 25°C and TA = 85°C, AV = 20, VS = ±110 V, RF = 100

kΩ, RADJ = 0 Ω

LFCSP PACKAGE AND HIGH VOLTAGE PIN

SPACING

A 7 mm × 7 mm, 12-lead LFCSP with EPAD was selected for the

ADHV4702-1 to provide high reliability and compliance to regional

and global high voltage standards regarding dielectric withstand-

ing (clearance) and carbonization of package surface (creepage).

The package dimensions are shown in Outline Dimensions. The

ADHV4702-1 meets the minimum 1.25 mm spacing requirement

of IEC Standard 61010-1 for creepage distance to preclude failure

due to carbon tracking at 250 V rms. To maintain these protections,

it is essential to remove all flux and soldering residue around the

package pins and exposed pad. Refer to the IEC 61010-1 standard

for additional information.

EXPOSED PAD (EPAD)

The copper EPAD of the LFCSP provides a thermally conductive

path to the PCB, which can be attached to a heat sink to improve

heat dissipation. There is no internal electrical connection to the

EPAD. High voltage isolation allows the EPAD to be safely biased

to a 0 V ground plane, regardless of VCC or VEE voltages.