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PIC18F44J10-E/SP Datenblatt(PDF) 89 Page - Microchip Technology |
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PIC18F44J10-E/SP Datenblatt(HTML) 89 Page - Microchip Technology |
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89 / 358 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39682C-page 87 PIC18F45J10 FAMILY REGISTER 8-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 REGISTER 8-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 OSCFIE CMIE — — BCL1IE — — CCP2IE bit 7 bit 0 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 =Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 =Disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module) 1 = Enabled 0 =Disabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 =Disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 SSP2IE BCL2IE — — — — — — bit 7 bit 0 bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module) 1 = Enabled 0 = Disabled bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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