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PIC18F44J10-E/SP Datenblatt(PDF) 91 Page - Microchip Technology |
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PIC18F44J10-E/SP Datenblatt(HTML) 91 Page - Microchip Technology |
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91 / 358 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39682C-page 89 PIC18F45J10 FAMILY REGISTER 8-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W1 U-0 U-0 R/W-1 U-0 U-0 R/W-1 OSCFIP CMIP — — BCL1IP — — CCP2IP bit 7 bit 0 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 =High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 =High priority 0 = Low priority bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module) 1 =High priority 0 = Low priority bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 =High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 SSP2IP BCL2IP — — — — — — bit 7 bit 0 bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module) 1 = High priority 0 = Low priority bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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