PTN3700 datasheet(8/41 Pages) PHILIPS

8 / 41 page

PTN3700_1

Product data sheet

Rev. 01 — 14 August 2007

8 of 41

NXP Semiconductors

PTN3700

1.8 V simple mobile interface link bridge IC

[1]

Depends on conﬁguration.

Table 4.

Pin description - Receiver mode

Symbol

Pin[1]

Type

Description

Parallel data outputs

R[7:0], G[7:0], B[7:0]

CMOS

8-bit wide R, G, B pixel data outputs

CMOS

Horizontal synchronization data output, active LOW

CMOS

Vertical synchronization data output, active LOW

CMOS

Data Enable output, active HIGH

A0, A1

CMOS

Auxiliary output bits

High-speed serial inputs

D0+, D0

−, D1+,

−, D2+, D2−

SubLVDS

receiver

Serialized high-speed differential subLVDS data inputs

CLK+, CLK

−

SubLVDS

receiver

Serialized high-speed differential subLVDS clock inputs

Clock outputs

PCLK

CMOS

Pixel clock output

Conﬁguration inputs

TX/RX

CMOS

Transmitter/Receiver conﬁguration input pin. When LOW, PTN3700 is conﬁgured

as receiver.

LS0, LS1

CMOS

Serialization mode program pins. Select between 1, 2 or 3 lanes. See Table 5.

PSEL0, PSEL1

CMOS

Pin mirroring select pins. See Table 6 and Table 7.

XSD

CMOS

Shutdown mode input pin, active LOW, puts PTN3700 in lowest-power mode by

deactivating all circuitry. When HIGH, PTN3700 is either in Active mode or

awaiting clock input (Standby mode).

F/XS

CMOS

Program pin for fast (F/XS = HIGH) or slow (F/XS = LOW) parallel output and

PCLK slew rate

CMOS

Frame Mixing select pin. When LOW, Frame Mixing is disabled and PTN3700

passes 24-bit video data transparently. When HIGH, Frame Mixing is enabled

and PTN3700 applies processing to the 24-bit video data resulting in 18-bit

output data words encoded with 24-bit color depth. Frame Mixing is only

available in Receiver mode.

FSS

CMOS

Fully Source Synchronous select pin. When LOW, PTN3700 uses pseudo source

synchronous serial reception mode with the pixel clock as both the reference

frequency and the frame boundary delineation. When HIGH, PTN3700 uses true

source synchronous reception with embedded synchronization word decoding,

with the bit clock as reference frequency. On both Receiver and Transmitter, the

settings of the FSS pin should match. Otherwise the link will not function.

Parity output

CPO

CMOS

Parity error output, active HIGH. A HIGH level indicates a parity error was

detected in the current pixel data

Power supply

VDD

power supply voltage

VDDA

analog (PLL) power supply voltage

GNDA

analog (PLL) ground

GND

ground

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