ADS8317IBDRBT datasheet(20/29 Pages) TI

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DIGITAL INTERFACE

Signal Levels

Data Format

Serial Interface

ADS8317

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

After the fifth falling DCLOCK edge, DOUT is enabled

and outputs a low value for one clock period. For the

DCLOCK

periods,

DOUT outputs

the

conversion result, most significant bit first. After the

The ADS8317 has a wide range of power-supply

least significant bit (B0) has been output, subsequent

voltage. The A/D converter, as well as the digital

clocks repeat the output data, but in a least significant

interface circuit, is designed to accept and operate

bit first format.

from

2.7V

5.5V.

This

voltage

range

accommodates

different

logic

levels.

When

the

After

the

most

significant

bit

(B15)

has

been

ADS8317 power-supply voltage is in the range of

repeated, DOUT will 3-state. Subsequent clocks have

4.5V to 5.5V (5V logic level), the ADS8317 can be

no effect on the converter. A new conversion is

connected directly to another 5V, CMOS-integrated

initiated only when CS has been taken high and

circuit. When the ADS8317 power-supply voltage is in

returned low.

the range of 2.7V to 3.6V (3V logic level), the

ADS8317 can be connected directly to another 3.3V

LVCMOS integrated circuit.

The output data from the ADS8317 are in binary twos

complement format, as shown in Table 1 and

Figure 44. The table and figure represent the ideal

The ADS8317 communicates with microprocessors

output code for the given input voltage and do not

and other digital systems via a synchronous 3-wire

include the effects of offset, gain error, or noise.

serial

interface,

illustrated

the

Timing

Information section and Timing Characteristics. The

Table 1. Ideal Input Voltages and Output Codes

DCLOCK signal synchronizes the data transfer, with

DESCRIPTION

ANALOG VALUE

DIGITAL OUTPUT

each bit being transmitted on the falling edge of

Full-scale range

× V

REF

BINARY TWOS COMPLEMENT

DCLOCK.

Most

receiving

systems

capture

the

Least significant

× V

REF/65536

Binary

Hex

bitstream on the rising edge of DCLOCK. However, if

bit (LSB)

Code

the minimum hold time for DOUT is acceptable, the

+Full scale

+VREF – 1 LSB

0111 1111 1111 1111

7FFF

system can use the falling edge of DCLOCK to

Midscale

0000 0000 0000 0000

0000

capture each bit.

Midscale – 1 LSB

0V – 1 LSB

1111 1111 1111 1111

FFFF

A falling CS signal initiates the conversion and data

–Full scale

–VREF

1000 0000 0000 0000

8000

transfer. The first 4.5 to 5.0 clock periods of the

conversion cycle are used to sample the input signal.

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