Internet Data Sheet

5

Rev.1.80, 2006-11

07092007-3E44-UTNM

HY[B/E]18M512160BF

512-Mbit DDR Mobile-RAM

Overview

1.3

Description

The HY[B/E]18M512160BF is a high-speed CMOS, dynamic random-access memory containing 536,870,912

bits. It is internally configured as a quad-bank DRAM.

The HY[B/E]18M512160BF uses a double-data-rate architecture to achieve high-speed operation. The double-

data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single READ or WRITE access for the DDR Mobile-RAM consists of a

single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-

half clock cycle data transfers at the I/O pins.

The HY[B/E]18M512160BF is especially designed for mobile applications. It operates from a 1.8V power supply.

Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can

further be reduced by using the programmable Partial Array Self Refresh (PASR).

A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-

Down (DPD) mode. For further power-savings the clock may be stopped during idle periods.

The HY[B/E]18M512160BF is housed in a 60-ball very thin FBGA package. It is available in Commercial (0°C to

Figure 2

Functional Block Diagram