Internet Data Sheet

3

Rev.1.80, 2006-11

07092007-3E44-UTNM

HY[B/E]18M512160BF

512-Mbit DDR Mobile-RAM

Overview

1Overview

1.1

Features

•

4 banks

× 8 Mbit × 16 organization

•

Double-data-rate architecture : two data transfers per clock cycle

•

Bidirectional data strobe (DQS) is transmitted / received with data; to be used in capturing data at the receiver

•

DQS is edge-aligned with data for READs and center-aligned with data for WRITEs

•

Differential clock input (CK / CK)

•

Commands entered on positive CK edge; data and mask data are referenced to both edges of DQS

•

Four internal banks for concurrent operation

•

Programmable CAS latency: 2 and 3

•

Programmable burst length: 2, 4, 8 and 16

•

Programmable drive strength (full, half, quarter)

•

Auto refresh and self refresh modes

•

8192 refresh cycles / 64ms

•

Auto precharge

•

•

60-ball Very Thin FBGA package (10.5

× 10.5 × 1.0 mm)

•

Power Saving Features

•

Low supply voltages:

V

•

Optimized operating (

I

•

DDR I/O scheme with no DLL

•

Programmable Partial Array Self Refresh (PASR)

•

Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor

•

Clock Stop, Power-Down and Deep Power-Down modes

1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and

electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council

of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated

biphenyls and polybrominated biphenyl ethers.

Table 1

Performance

Part Number Speed Code

- 6

- 7.5

Unit

Clock Frequency (

f

CL = 3

166

133

MHz

CL = 2

83

66

MHz

Access Time (

t

6.5

ns

Table 2

Memory Addressing Scheme

Item

Addresses

Banks

BA0, BA1

Rows

A0 - A12

Columns

A0 - A9