TMPR4937 datasheet(62/552 Pages) TOSHIBA

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Chapter 3 Signals

3-8

3.1.11 Extended EJTAG Interface Signals

Table 3.1.11 Extended EJTAG Interface Signals

Signal Name

Type

Description

Initial State

TCK

Input

JTAG Test Clock Input

Clock input signal for JTAG.

TCK is used to execute JTAG instructions and input/output data.

Input

TDI/DINT*

Input

JTAG Test Data Input/Debug Interrupt

When PC trace mode is not selected, this signal is a JTAG data input signal. It is used to

input serial data to JTAG data/instruction registers.

When PC trace mode is selected, this signal is an interrupt input signal used to cancel

PC trace mode for the debug unit.

Input

TDO/TPC[0]

Output

JTAG Test Data Output/PC Trace Output

When PC trace mode is not selected, this signal is a JTAG data output signal. Data is

output by means of serial scan.

When PC trace mode is selected, this signal outputs the value of the non-continuous

program counter in sync with the debug clock (DCLK).

High

TPC[3:1]

Output

PC Trace Output

TPC[3:1] output the value of the noncontiguous program counter in sync with DCLK.

These signals are common with the other functions (refer to Section “3.3 Pin multiplex”).

Use the configuration setting during boot-up.

All High

TMS

Input

JTAG Test Mode Select Input

TMS mainly controls state transition in the TAP controller state machine.

Input

TRST*

Input

Test Reset Input

Asynchronous reset input for the TAP controller and debug support unit (DSU).

TRST* pin must be pulled down (ex.10 k

Ω).

When this signal is deasserted, G-Bus timeout detection is disabled (refer to Section

“5.1.1 Detecting G-Bus Timeout”).

Input

DCLK

Output

Debug Clock

Clock output signal for the real-time debugging system.

When PC trace mode is selected, the TPC[3:1] and PCST signals are output

synchronously. This clock is the TX49/H3 core operating clock (CPUCLK) divided by 3.

This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use

the configuration setting during boot-up.

Low

PCST[8:0]

Output

PC Trace Status Information

Outputs PC trace status and other information.

These signals are common with the other functions (refer to Section “3.3 Pin multiplex”).

Use the configuration setting during boot-up.

All Low

3.1.12 Clock Signals

Table 3.1.12 Clock Signals

Signal Name

Type

Description

Initial State

MASTERCLK

Input

Master Clock

Input pin for the TX4937 operating clock. A crystal resonator cannot be connected to this

pin because the pin does not contain an oscillator.

Input

HALTDOZE

Output

Halt/Doze State Output

This signal is asserted (High output) when the TX4937 enters Halt or Doze mode.

Low

BYPASSPLL*

Input

Bypass PLL

This pin must be fixed to High.

Input

CGRESET*

Input

CG Reset

CGRESET* initializes the CG.

Input

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