TMPR4937 datasheet(67/552 Pages) TOSHIBA

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Chapter 3 Signals

3-13

Table 3.2.3 Boot Configuration Specified with the DATA[22:0] Signals

Signal

Description

Corresponding

Configuration

Determined at

DATA[22:16]

Reserved

⎯

DATA[15:8]

Boot Configuration

Reads the board information and accordingly sets the boot

configuration field (BCFG) of the chip configuration register (CCFG).

CCFG.BCFG

RESET* deassert edge

DATA[7]

TX49/H3 Internal Timer Interrupt Disable

Specifies whether timer interrupts within the TX49/H2 core are

enabled.

H = Enable timer interrupts within the TX49/H3 core.

L = Disable timer interrupts within the TX49/H3 core.

CCFG.TINTDIS

RESET* deassert edge

DATA[6]

Reserved

⎯

DATA[5]

Specifies the function of the BE[3:0]*/BWE[3:0]* pins upon booting.

L = BE[3:0]* (Byte Enable)

H = BWE[3:0]* (Byte Write Enable)

EBCCR0.BC

RESET* deassert edge

DATA[4]

Boot ACK* Input

Specifies the access mode for external bus controller channel 0.

L = External ACK mode

H = Normal mode

EBCCR0.WT[0]

RESET* deassert edge

DATA[3]

Reserved

⎯

DATA[2]

PCI Arbiter Select

Selects a PCI bus arbiter.

L = External PCI bus arbiter.

H = Built-in PCI bus arbiter.

CCFG.PCIARB

RESET* deassert edge

DATA[1:0]

Boot ROM Bus Width

Specifies the data bus width when booting from a memory device

connected to the external bus controller.

LL = Reserved

LH = 32 bits

HL = 16 bits

HH = 8 bits

EBCCR0.BSZ

RESET* deassert edge

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