DAC5662MPFBREP datasheet(4/31 Pages) TI2

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DAC5662-EP

SGLS340A – JUNE 2006 – REVISED OCTOBER 2006

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

AGND

Analog ground

AVDD

Analog supply voltage

BIASJ_A

Full-scale output current bias for DACA

BIASJ_B

Full-scale output current bias for DACB

CLKA/CLKIQ

Clock input for DACA, CLKIQ in interleaved mode

CLKB/RESETIQ

Clock input for DACB, RESETIQ in interleaved mode

DA[11:0]

1–12

Data port A. DA11 is MSB and DA0 is LSB.

DB[11:0]

23–34

Data port B. DB11 is MSB and DB0 is LSB.

DGND

15, 21

Digital ground

DVDD

16, 22

Digital supply voltage

EXTIO

I/O

Internal reference output (bypass with 0.1

µF to AGND) or external reference input

GSET

Gain-setting mode: H = 1 resistor, L = 2 resistors. Internal pullup

IOUTA1

DACA current output. Full scale with all bits of DA high.

IOUTA2

DACA complementary current output. Full scale with all bits of DA low.

IOUTB1

DACB current output. Full scale with all bits of DB high.

IOUTB2

DACB complementary current output. Full scale with all bits of DB low.

MODE

Mode select: H = dual bus, L = interleaved. Internal pullup.

13, 14, 35,

–

No connection

Sleep function control input: H = DAC in power-down mode, L = DAC in operating mode.

SLEEP

Internal pulldown.

WRTA/WRTIQ

Input write signal for PORT A (WRTIQ in interleaving mode)

WRTB/SELECTIQ

Input write signal for PORT B (SELECTIQ in interleaving mode)

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