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ELECTRICAL CHARACTERISTICS

DAC5662-EP

SGLS340A – JUNE 2006 – REVISED OCTOBER 2006

over operating free-air temperature range, AVDD = DVDD = 3.3 V, I

OUTFS = 20 mA, independent gain set mode

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC Specifications

Resolution

12

Bits

DC Accuracy(1)

INL

Integral nonlinearity

1 LSB = IOUTFS/212, TA = 25°C

–2

  0.3

2

LSB

DNL

Differential nonlinearity

1 LSB = IOUTFS/212, TA = 25°C

–2

  0.2

2

LSB

Analog Output

Offset error

0.03

%FSR

With external reference

  0.25

%FSR

Gain error

With internal reference

  0.5

%FSR

Minimum full-scale output current(2)

2

mA

Maximum full-scale output current(2)

20

mA

Gain mismatch

With internal reference

–2

0.07

2

%FSR

Output voltage compliance range(3)

–0.8

1.25

V

RO

Output resistance

300

k

Ω

CO

Output capacitance

5

pF

Reference Output

Reference voltage

1.14

1.2

1.26

V

Reference output current(4)

100

nA

Reference Input

VEXTIO

Input voltage

0.1

1.25

V

RI

Input resistance

1

M

Ω

Small signal bandwidth

300

kHz

CI

Input capacitance

100

pF

Temperature Coefficients

ppm of

Offset drift

0

FSR/

°C

With external reference

±50

ppm of

Gain drift

FSR/

°C

With internal reference

±50

Reference voltage drift

±20

ppm/

°C

(1)

Measured differentially through 50

Ω to AGND.

(2)

Nominal full-scale current, IOUTFS, equals 32× the IBIAS current.

(3)

The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,

resulting in reduced reliability of the DAC5662 device. The upper limit of the output compliance is determined by the load resistors and

full-scale output current. Exceeding the upper limit adversely affects distortion performance and intergral nonlinearity.

(4)

Use an external buffer amplifier with high impedance input to drive any external load.

7

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