ADR6

bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

1

0

1

0

1

0

0

I2 C SLAVE address (chip address)

27

LP55281

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SNVS458D – JUNE 2007 – REVISED OCTOBER 2016

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Programming (continued)

In addition to the first start condition, a repeated start condition can be generated in the middle of a transaction.

This allows another device to be accessed or a register read cycle.

7.5.2.3 Acknowledge Cycle

The acknowledge cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

7.5.2.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to theacknowledge after every byte rule. When the master is the receiver, it must indicate

to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the

slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the

SDA line is not pulled down.

7.5.2.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP55281 operates as a slave device with 7-bit address.

LP55281 I2C address is pin selectable from two different choices. The LP55281 address is 4Ch (SI/A0 = 0) or

4Dh (SI/A0 = 1) as selected with SI/A0 pin. If eighth bit is used for programming, the 8th bit is 1 for read and 0 for

write.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device

should send an acknowledge signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a start condition. The direction of the data transfer (R/W) depends

on the bit sent after the slave address (the eighth bit).

When the slave address is sent, each device in the system compares this slave address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the

R/W bit (1 for read, 0 for write), the device acts as a transmitter or a receiver.

Figure 23. I2C Device Address