FN8808 datasheet(41/44 Pages) RENESAS

41 / 44 page

ISL78227

FN8808 Rev.6.02

Page 41 of 43

Feb 28, 2025

Layout Considerations

For DC/DC converter design, the PCB layout is very important to

ensure the desired performance.

1. Place input ceramic capacitors as close as possible to the IC's

VIN and PGND/SGND pins.

2. Place the output ceramic capacitors as close as possible to

the power MOSFETs. Keep this loop (output ceramic capacitor

and MOSFETs for each phase) as small as possible to reduce

voltage spikes induced by the trace parasitic inductances

when MOSFETs switching ON and OFF.

3. Place the output aluminum capacitors close to the power

MOSFETs.

4. Keep the phase node copper area small, but large enough to

handle the load current.

5. Place the input aluminum and some ceramic capacitors close

to the input inductors and power MOSFETs.

6. Place multiple vias under the bottom pad of the IC. Connect

the bottom pad to the ground copper plane with as large an

area as possible in multiple layers to effectively reduce the

thermal impedance. Figure 67 shows the layout example for

vias in the IC bottom pad.

7. Place the 10µF decoupling ceramic capacitor at the PVCC pin

and as close as possible to the IC. Put multiple vias close to

the ground pad of this capacitor.

8. Place the 1µF decoupling ceramic capacitor at the VCC pin

and as close as possible to the IC. Put multiple vias close to

the ground pad of this capacitor.

9. Keep the bootstrap capacitors as close as possible to the IC.

10. Keep the driver traces as short as possible and with relatively

large width (25 mil to 40 mil is recommended), and avoid

using via or minimal number of vias in the driver path to

achieve the lowest impedance.

11. Place the current sense setting resistors and the filter

capacitors (shown as RSETxB, RBIASxB, and CISENx in

Figure 60 on page 31) as close as possible to the IC. Keep

each pair of the traces close to each other to avoid undesired

switching noise injections.

12. The current-sensing traces must be laid out very carefully

because they carry tiny signals with only tens of mV.

For the current-sensing traces close to the power sense

resistor (RSENx), the layout pattern shown in Figure 68 is

recommended. Assuming the RSENx is placed in the top layer

(red), route one current sense connection from the middle of

one RSENx pad in the top layer under the resistor (red trace).

For the other current-sensing trace, from the middle of the

other pad on RSENx in the top layer, after a short distance, via

down to the second layer and route this trace right under the

top layer current sense trace.

13. Keep the current-sensing traces far from the noisy traces such

as gate driving traces (LGx, UGx, and PHx), phase nodes in

power stage, BOOTx signals, output switching pulse currents,

driving bias traces, and input inductor ripple current signals,

etc.

FIGURE 67. RECOMMENDED LAYOUT PATTERN FOR VIAS IN THE

IC BOTTOM PAD

FIGURE 68. RECOMMENDED LAYOUT PATTERN FOR CURRENT

SENSE TRACES REGULATOR

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