FN8808 datasheet(28/44 Pages) RENESAS

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ISL78227

FN8808 Rev.6.02

Page 28 of 43

Feb 28, 2025

Figure 55 shows the relationship between RFSYNC and switching

frequency.

The ISL78227 contains a Phase Lock Loop (PLL) circuit.

Referring to Figure 4 on page 8, the PLL is compensated with a

series resistor-capacitor (RPLL and CPLL1) from the PLLCOMP pin

to GND and a capacitor (CPLL2) from PLLCOMP to GND. At the

300kHz switching frequency, typical values are RPLL = 3.24kΩ,

CPLL1 = 6.8nF, and CPLL2 = 1nF. The PLL locking time is around

0.7ms. Generally, the same PLL compensating network can be

used in the frequency range of 50kHz to 1.1MHz. With the same

PLL compensation network, at a frequency range higher than

500kHz, the PLL is overcompensated. However, the PLL is stable

just with slow frequency response. If a faster frequency response

is required at a higher operating frequency, the PLL

compensation network can be tuned to have a faster response.

An Excel spreadsheet to calculate the PLL compensation is

provided on the ISL78227 product page.

The ISL78227’s switching frequency can be synchronized to the

external clock signals applied at the FSYNC pin. The ISL78227

detects the input clock’s rising edge and synchronizes the rising

edge of LG1 to the input clock’s rising edge with a dead time

delay of tDT1. The switching frequency of each phase equals the

fundamental frequency of the clock input at FSYNC. Because the

ISL78227 detects only the edge of the input clock instead of its

pulse width, the input clock’s pulse width can be as low as 20ns

(as minimum), tens of ns, or hundreds of ns, depending on the

capability of the specific system to generate the external clock.

The CLKOUT pin outputs a clock signal with the same frequency

of the per-phase switching frequency. Its amplitude is VCC and

the pulse width is 1/12 of the per-phase switching period

(tSW/12). Figure 56 shows the application example to put two

ISL78227s in parallel for 4-phase, interleaved operation, with the

master IC’s CLKOUT being connected to the FSYNC pin of the

slave IC. The master IC outputs CLKOUT signal with a delay of

tSW/4 - tDT1 after LG1_master. The slave IC FSYNC pin takes the

CLKOUT_master as the input and the slave’s IC LG1 is delayed by

a time of 35ns + tDT1. Therefore, the LG1_slave is delayed by

tSW/4+35ns to LG1_master, which is approximately a 90° phase

shift. With 90°phase shift between LG1 and respective LG2 for

each IC, an interleaved 4-phases with 90° phase shift boost is

achieved.

After the ISL78227 latches to being synchronized with the

external clock, if the external clock on the FSYNC pin is removed,

the switching frequency oscillator shuts down. The part then

detects PLL_LOCK fault (refer to Table 3 on page 34), and goes to

either Hiccup mode or Latch-off mode, depending on the

HIC/LATCHOFF pin configuration. If the part is set in Hiccup

mode, it restarts with frequency set by the resistor at the FSYNC

pin.

The switching frequency range of the ISL78227 set by RFSYNC or

by synchronization is typically 50kHz to 1.1MHz.

The low end 50kHz is determined by a PLL_LOCK fault

protection, which shuts down the IC when frequency is lower than

37kHz typical.

The phase dropping mode is not allowed with external

synchronization.

MINIMUM ON-TIME (BLANK TIME) CONSIDERATION

The minimum ON-time (also called BLANK time) of LGx is the

minimum ON pulse width as long as LGx is turned ON. It is also

intended for the internal circuits to blank out the noise spikes

after LGx turns on. The tMINON can be programmed by a resistor

at the RBLANK pin.

The selection of the tMINON depends on two considerations.

1. The noise spike durations after LGx turns on, which is

normally in a range of tens of ns to 100ns or longer,

depending on the external MOSFET switching characteristic

and noise coupling path to current sensing.

2. Ensure the charging of the boot capacitor during operations of

LGx operating at tMINON. One typical case is an operation

when the input voltage is close to the output voltage. The duty

cycle is smallest at tMINON, and CBOOTx is charged by PVCC

via DBOOTx with short duration of tMINON minus the delay to

pull phase low. If such operation is required, especially when

a large MOSFET with large Qg is used to support heavy load

application, larger tMINON can be programmed with the

resistor at the RBLANK pin to ensure CBOOTx can be

sufficiently charged during minimum duty cycle operation.

100

150

200

250

300

100 200

300

400

500

600 700

800

900 100 0 110 0

f SW (kHz)

FIGURE 55. fSW vs RFS

FIGURE 56. TIMING DIAGRAM OF CLKOUT vs LG1 AND FSYNC vs LG1

(CLKOUT_MASTER CONNECTED TO FSYNC_SLAVE)

LG1_IC_Master

CLKOUT_IC_Master

FSYNC_IC_Slave

LG1_IC_Slave

tSW/4 - tDT1

t1 t2 t3

35ns + tDT1

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