AM486DE2 datasheet(2/52 Pages) AMD

2 / 52 page

Am486DE2 Microprocessor

BLOCK DIAGRAM

ADS, W/R, D/C, M/IO,

PCD, PWT, RDY, LOCK,

PLOCK, BOFF, A20M,

BREQ, HOLD, HLDA,

RESET, INTR, NMI,

FERR, UP, IGNNE, SMI,

SMIACT, SRESET

Control

ROM

Floating-

Point

File

Floating-

Point

Unit

Micro-instruction

Decoded

Instruction

Path

Instruction

Decode

Code

Stream

Displacement Bus

32-Byte

Code Queue

2x16 Bytes

Prefetcher

128

JTAG

TDI, TCK,

TDO, TMS

PCHK,

DP3–DP0

Parity

Generation

and Control

Cache

Control

KEN, FLUSH,

AHOLD, CACHE,

EADS, INV,

WB/WT, HITM

BS16, BS8

Bus Size

Control

Burst Bus

Control

BRDY, BLAST

Bus Control

Request

Sequencer

Data Bus

Transceivers

D31–D0

Writeback

Buffers

4x32

Copyback

Buffers

4x32

Write

Buffers

4x32

Address

Drivers

A31–A2

BE3–BE0

Bus Interface

Clock

Generator

CLK

STPCLK

Clock

Interface

32-Bit Data Bus

32-Bit Linear Address

Barrel

Shifter

File

ALU

Physical

Address

Segmentation

Unit

Descriptor

Registers

Limit and

Attribute

PLA

Paging Unit

Translation

Lookaside

Buffer

PCD, PWT

Physical

Address

8-Kbyte

Cache

Cache Unit

Central and

Protection

Test Unit

VOLDET

V, V

Power

Plane

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