AM486DE2 datasheet(13/52 Pages) AMD

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Am486DE2 Microprocessor

is ignored when the bus is idle and at the end of the first

clock in a bus cycle. BRDY is sampled in the second

and subsequent clocks of a burst cycle. The data pre-

sented on the data bus is strobed into the microproces-

sor when BRDY is sampled active. If RDY is returned

simultaneously with BRDY, BRDY is ignored and the

cycle is converted to a non-burst cycle. BRDY is active

Low and has a small pull-up resistor, and must satisfy

the setup and hold times t16 and t17.

BREQ

Internal Cycle Pending (Output)

BREQ indicates that the microprocessor has generated

a bus request internally, whether or not the micropro-

cessor is driving the bus. BREQ is active High and is

floated only during Three-state Test mode. (See

FLUSH.)

BS8/BS16

Bus Size 8 (Active-Low Input)

Bus Size 16 (Active-Low Input)

The BS8 and BS16 signals allow the processor to oper-

ate with 8-bit and 16-bit I/O devices by running multiple

bus cycles to respond to data requests: four for 8-bit

devices, and two for 16-bit devices. The bus sizing pins

are sampled every clock. The microprocessor samples

the pins every clock before RDY to determine the ap-

propriate bus size for the requesting device. The signals

are active Low input with internal pull-up resistors, and

must satisfy setup and hold times t

14 and t15 for correct

operation. Bus sizing is not permitted during copy-back

or write-back operation. BS8 and BS16 are ignored dur-

ing copy-back or write-back cycles.

CACHE (New)

Internal Cacheability (Active-Low Output)

In Write-through mode, this signal always floats.

CLK (Modified)

Clock (Input)

The CLK input provides the basic microprocessor timing

signal. All external timing parameters are specified with

respect to the rising edge of CLK. The clock signal pass-

es through an internal Phase-Lock Loop (PLL). The CLK

input is multiplied by two by an internal phase lock loop

(PLL) to generate the internal operating frequency.

D31–D0

Data Lines (Inputs/Outputs)

Lines D31–D0 define the data bus. The signals must

meet setup and hold times t

22 and t23 for proper read

operations. These pins are driven during the second and

subsequent clocks of write cycles.

D/C

Data/Control (Output)

This bus cycle definition pin distinguishes memory and

I/O data cycles from control cycles. The control cycles

are:

s Interrupt Acknowledge

s Halt/Special Cycle

s Code Read (instruction fetching)

DP3–DP0

Data Parity (Inputs/Outputs)

Data parity is generated on all write data cycles with the

same timing as the data driven by the microprocessor.

Even parity information must be driven back into the

microprocessor on the data parity pins with the same

timing as read information to ensure that the processor

uses the correct parity check. The signals read on these

pins do not affect program execution. Input signals must

meet setup and hold times t22 and t23. DP3–DP0 should

be connected to VCC through a pull-up resistor in systems

not using parity. DP3–DP0 are active High and are driven

during the second and subsequent clocks of write cycles.

EADS (Modified)

External Address Strobe (Active-Low Input)

This signal indicates that a valid external address has

been driven on the address pins A31–A4 of the micro-

processor to be used for a cache snoop. This signal is

recognized while the processor is in hold (HLDA is driv-

en active), while forced off the bus with the BOFF input,

or while AHOLD is asserted. The microprocessor ig-

nores EADS at all other times. EADS is not recognized

during the clock after ADS, nor during the clock after a

valid assertion of EADS. Snoops to the on-chip cache

must be completed before another snoop cycle is initi-

ated. Table 1 describes EADS when first sampled.

EADS can be asserted every other clock cycle as long

as the hold remains active and HITM remains inactive.

INV is sampled in the same clock period that EADS is

asserted. EADS has an internal weak pull-up.

Table 1. EADS Sample Time

Trigger

EADS First Sampled

AHOLD

Second clock after AHOLD asserted

HOLD

First clock after HLDA asserted

BOFF

Second clock after BOFF asserted

Note: The triggering signal (AHOLD, HOLD, or BOFF) must

remain active for at least 1 clock after EADS to ensure proper

operation.

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