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TLV702 Datenblatt(PDF) 11 Page - Texas Instruments

Teilenummer TLV702
Bauteilbeschribung  TLV702-Q1 300-mA, Low-IQ, Low-Dropout Regulator
PDF  36 Pages
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Hersteller  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TLV702 Datenblatt(HTML) 11 Page - Texas Instruments

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Thermal
Shutdown
Current
Limit
UVLO
Bandgap
IN
EN
OUT
LOGIC
GND
TLV702-Q1 Series
11
TLV702-Q1
www.ti.com
SLVSC35D – AUGUST 2013 – REVISED JULY 2019
Product Folder Links: TLV702-Q1
Submit Documentation Feedback
Copyright © 2013–2019, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The TLV702-Q1 series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent
line and load transient performance. These LDOs are designed for power-sensitive applications. A precision
bandgap and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection
ratio (PSRR), and low dropout voltage make this series of devices ideal for most battery-operated handheld
equipment. All device versions have integrated thermal shutdown, current limit, and undervoltage lockout (UVLO)
protections.
7.2 Functional Block Diagrams
Figure 23. TLV702-Q1 Block Diagram
7.3 Feature Description
7.3.1 Internal Current Limit
The TLV702-Q1 internal current limit protection helps to protect the regulator during fault conditions. During
current limit operation, the output sources a fixed amount of current that is largely independent of the output
voltage. In such a case, the output voltage is not regulated, and is VOUT = ICL × RLOAD. The PMOS pass transistor
dissipates (VIN – VOUT) × ICL until thermal shutdown is triggered and the device turns off. As the device cools, the
device is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles
between current limit operation and thermal shutdown. See Thermal Consideration for more details.
The PMOS pass element in the TLV702-Q1 has a built-in body diode that conducts current when the voltage at
the OUT pin exceeds the voltage at IN. This current is not limited; if extended reverse-voltage operation is
anticipated, externally limit the output current to 5% of the rated IOUT specification.



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