ADS5500-EP

SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008

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9

RESET TIMING CHARACTERISTICS

Typ, min, and max values at TA = 25°C, min and max specified over the full recommended operating temperature range,

AVDD = DRVDD = 3.3 V, 3−VPP differential clock (unless otherwise noted)

PARAMETER

DESCRIPTION

TYP

UNIT

Switching Specification

Power−up time

Delay from power−up of AVDD and DRVDD to output

stable

40

ms

SERIAL PROGRAMMING INTERFACE CHARACTERISTICS

The device has a three-wire serial interface. The device

latches the serial data SDATA on the falling edge of

serial clock SCLK when SEN is active.

D Serial shift of bits is enabled when SEN is low.

SCLK shifts serial data at falling edge.

D Minimum width of data stream for a valid loading is

16 clocks.

D Data is loaded at every 16th SCLK falling edge

while SEN is low.

D In case the word length exceeds a multiple of

16 bits, the excess bits are ignored.

D Data can be loaded in multiple of 16-bit words within

a single active SEN pulse.

A3

ADDRESS

SDATA

MSB

DATA

A2

A1

A0

D11

D10

D9

D0

Figure 3. DATA Communication Is 2 Byte, MSB First

tSLOADS

tWSCLK

tOS

tOH

tWSCLK

tSCLK

16 x M

MSB

LSB

LSB

MSB

tSLOADH

SCLK

SEN

SDATA

Figure 4. Serial Programming Interface Timing Diagram

Table 1. Serial Programming Interface Timing Characteristics

SYMBOL

PARAMETER

MIN(1)

TYP(1)

MAX(1)

UNIT

tSCLK

SCLK period

50

ns

tWSCLK

SCLK duty cycle

25%

50%

75%

tSLOADS

SEN to SCLK setup time

8

ns

tSLOADH

SCLK to SEN hold time

6

ns

tDS

Data setup time

8

ns

tDH

Data hold time

6

ns

(1) Min, typ, and max values are characterized, but not production tested.