ADS5400IPZP datasheet(24/58 Pages) TI2

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Analog Input Amplitude − dBFS

−25

−20

−15

−10

−5

−1

G023

After Positive

Over-range

1GSPS (1ns)

After Negative

Over-range

1GSPS (1ns)

After Positive

Over-range

400MSPS (2.5ns)

After Positive

Over-range

200MSPS (5ns)

After Negative

Over-range

400MSPS (2.5ns)

After Negative

Over-range

200MSPS (5ns)

ADS5400

SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

www.ti.com

Feature Description (continued)

7.3.3 Analog Input Over-Range Recovery Error

An over-range condition occurs if the analog input voltage exceeds the full-scale range of the converter (0 dBFS).

To test recovery from an over-range, the ADC analog input is injected with a sinusoidal input frequency exactly at

CLKIN/4 (a four-point sinusoid at the digital outputs). The four sample points of each period occur at the top, mid-

scale, bottom and mid-scale of the sinusoid (clipped by the ADC when over-ranged to all 0s or all 1s). Once the

amplitude exceeds 0dBFS, the top and bottom of the sinusoidal input becomes out of range, while the mid-scale

point is always in-range and measureable with ADC output codes. The graph in Figure 27 indicates the amount

of error from the expected mid-scale value of 2048 that occurs after negative over-range (bottom of sinusoid) and

positive over-range (top of sinusoid). This equates to the amount of error in a valid sample 1 clock cycle after an

over-range occurs, as a function of input amplitude.

Figure 27. Recovery Error 1 Clock Cycle After Over-Range vs Input Amplitude

7.3.4 Clock Inputs

The ADS5400 clock input can be driven with either a differential clock signal or a single-ended clock input. The

equivalent clock input circuit can be seen in Figure 28. In low-input-frequency applications, where jitter may not

be a big concern, the use of a single-ended clock (as shown in Figure 29) could save cost and board space

without much performance tradeoff. When clocked with this configuration, it is best to connect CLK to ground

with a 0.01-

μF capacitor, while CLK is ac-coupled with a 0.01-μF capacitor to the clock source, as shown in

Figure 29.

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