REF2925 datasheet(27/62 Pages) TI2

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D17

D16

DOUT

SCLK

CONVST

1/fsample

tACQ

tconv-max

Acquiring

Sample N

Converting

Sample N

End-of-

Conversion

ADC

STATE

tconv-min

DIN

Acquiring Sample N+1

Read Sample N

DIN = 1

CNV

SDI

CLK

DIN

CONVST

DOUT

SCLK

ADC

Digital Host

ADS8881

www.ti.com

SBAS547D – MAY 2013 – REVISED AUGUST 2015

Product Folder Links: ADS8881

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Device Functional Modes (continued)

10.4.1.3 4-Wire CS Mode Without a Busy Indicator

This interface option is useful when one or more ADCs are connected to an SPI-compatible digital host.

Figure 54 shows the connection diagram for single ADC; see Figure 56 for the connection diagram for two ADCs.

Figure 54. Connection Diagram: Single ADC With 4-Wire CS Mode Without a Busy Indicator

In this interface option, DIN is controlled by the digital host and functions as CS. As shown in Figure 55, with DIN

high, a CONVST rising edge selects CS mode, forces DOUT to 3-state, samples the input signal, and causes the

device to enter a conversion phase. In this interface option, CONVST must be held at a high level from the start

of the conversion until all data bits are read. Conversion is done with the internal clock and continues regardless

of the state of DIN. As a result, DIN (functioning as CS) can be pulled low to select other devices on the board.

However, DIN must be pulled high before the minimum conversion time (tconv-min) elapses and remains high until

the maximum possible conversion time (tconv-max) elapses. A high level on DIN at the end of the conversion

ensures the device does not generate a busy indicator.

Figure 55. Interface Timing Diagram: Single ADC With 4-Wire CS Mode

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