STA381BWS datasheet(65/174 Pages) STMICROELECTRONICS

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STA381BWS

To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any

audio streams flowing into the STA381BWS data path before the desynchronization event

happens. At the same time any processing related to the I2C configuration should be issued

only after the serial audio interface and the internal PLL are synchronous again.

Note:

Any mute or volume change causes some delay in the completion of the I2C operation due

to the soft volume feature. The soft volume phase change must be finished before any clock

desynchronization.

6.14.3

Delay serial clock enable

6.14.4

Channel input mapping

Each channel received via I2S can be mapped to any internal processing channel via the

channel input mapping registers. This allows for flexibility in processing. The default settings

of these registers map each I2S input channel to its corresponding processing channel.

6.15

Configuration register C (addr 0x13)

6.15.1

FFX compensating pulse size register

Table 35. Delay serial clock enable

Bit

R/W

RST

Name

Description

R/W

DSCKE

0: No serial clock delay

1: Serial clock delay by 1 core clock cycle to tolerate

anomalies in some I2S master devices

Table 36. Channel input mapping

Bit

R/W

RST

Name

Description

R/W

C1IM

0: Processing channel 1 receives left I2S input

1: Processing channel 1 receives right I2S input

R/W

C2IM

0: Processing channel 2 receives left I2S input

1: Processing channel 2 receives right I2S input

Reserved

CSZ3

CSZ2

CSZ1

CSZ0

Reserved

10010111

Table 37. FFX compensating pulse size bits

Bit

R/W

RST

Name

Description

R/W

CSZ0

When OM[1,0] = 11, this register determines the size

of the FFX compensating pulse from 0 clock ticks to

15 clock periods.

R/W

CSZ1

R/W

CSZ2

R/W

CSZ3

Obsolete

Product(s)

- Obsolete

Product(s)

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