button/ACK frequency, and the third to differentiate between an authentication sequence and a button press.

The third sample is taken 2.89ms after the second sample. If the specially enabled audio interface reads the

ACK frequency during the third sample, the interface acknowledges a proper authentication sequence. If the

tone frequency is not present during the third sample, the specially enabled audio interface recognizes the tone

sequence as a button tone. When a button tone is recognized any time after the timeout period, the specially

enabled audio interface records a button press event.

7.3.3 Shunt Regulator

An internal shunt regulator in the CD326x isolates the internal circuitry power supply from the MIC pin. The shunt

regulator can provide power to an external microphone module through the MICPWR pin, or the MICPWR output

can be used as an enable signal to control power to an external microphone module as shown in Figure 8-1. The

CD326x regulates the MICPWR output to approximately 1.56V. The shunt regulator only regulates the VSHUNT

and MICPWR pins during tone mode. During button mode operation, the CD326x powers down the regulator.

An external resistance between the MIC and VSHUNT pins determines the current into the VSHUNT pin. The

shunt regulator requires current of at least 93µA to maintain regulation of the VSHUNT pin. Any excess current

becomes available to the load at MICPWR. Any further excess current is internally shunted to ground.

7.3.4 Power-on-reset

The CD326x has an internal power-on-reset (POR) circuit that holds all internal logic in a predetermined reset

state until the supply voltage reaches a valid operating level and all internal nodes have stabilized. Figure 7-3

illustrates POR operation.

While the MIC pin is below VLVALID (200mV typical), POR is in an indeterminate state. When the supply voltage

on the MIC pin is greater than VLVALID, the POR circuit asserts low until the supply rises to VPOR-RISE (1.2V

typical). When the supply reaches VPOR-RISE, the POR function enters a valid operating supply state, and the

POR signal remains asserted low for a predetermined delay tDPOR (1ms typical).

The POR function remains in the valid operating supply state until the supply voltage on the MIC pin falls

below VPOR-FALL (0.8V typical). Upon falling below this threshold, the POR circuit immediately asserts the POR

signal and enters the original low-supply state until a valid operating supply voltage is supplied. When the POR

circuit recognizes a low-supply voltage during tDPOR, the circuit immediately resets the delay timer, maintains the

asserted POR signal, and enters the low-supply state. After a valid operating supply voltage is reached again,

the POR circuit repeats the operation.

Logic Status

RESET

RESET

ACTIVE

ACTIVE

X

VPOR-RISE

VPOR-FALL

VLVALID

tDPOR

1ms

Time

MIC

POR

tDPOR

1ms

0.8

1.2

0.2

Figure 7-3. Power-on-reset (POR) Logic Signal

CD3268A, CD3269A

SCHS463 – MAY 2025

www.ti.com

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