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LP55231 Datenblatt(PDF) 17 Page - Texas Instruments

Teilenummer LP55231
Bauteilbeschribung  LP55231 Nine-Channel RGB, White-LED Driver With Internal Program Memory and Integrated Charge Pump - WQFN
PDF  59 Pages
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Hersteller  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
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LP55231 Datenblatt(HTML) 17 Page - Texas Instruments

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STANDBY
RESET
INTERNAL
STARTUP
SEQUENCE
Reset Register = FF
or
POR=H
TSD = H
NORMAL MODE
EN=H (pin) and
CHIP_EN=H (bit)
EN=L (pin) or
CHIP_EN=L (bit)
POR
TSD = L
POWER SAVE
Enter power save
Exit power save
17
LP55231
www.ti.com
SNOSCR5D – MARCH 2013 – REVISED DECEMBER 2016
Product Folder Links: LP55231
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
7.4 Device Functional Modes
7.4.1 Modes Of Operation
RESET:
In the RESET mode all the internal registers are reset to the default values. Reset is always
entered if Reset Register (3DH) is written FFH or internal Power-On Reset is active. Power-On
Reset (POR) activate during the chip start-up or when the supply voltage VDD fall below 1.5 V
(typical). Once VDD rises above 1.5 V (typical), POR deactivate, and the chip continues to the
STANDBY mode. CHIP_EN control bit is low after POR by default.
STANDBY: The STANDBY mode is entered if the register bit CHIP_EN or EN pin is LOW and Reset is not
active. This is the low-power consumption mode, when all circuit functions are disabled. Most
registers can be written in this mode if EN pin is risen to high so that control bits are effective right
after the start-up (see Control Register Details).
START-UP: When CHIP_EN bit is written high, and EN pin is high, the INTERNAL START-UP SEQUENCE
powers up all the needed internal blocks (VREF, Bias, Oscillator etc.). Start-up delay is 500 μs. If
the chip temperature rises too high, the Thermal Shutdown (TSD) disables the chip operation, and
the chip waits in START-UP mode until no thermal shutdown event is present.
NORMAL:
During NORMAL mode the user controls the chip using the Control Registers.
POWER SAVE: In POWER-SAVE mode analog blocks are disabled to minimize power consumption. See
Automatic Power-Save Mode section for further information.
Figure 19. Modes of Operation



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