ADRF5702BCCZN-R7 datasheet(26/27 Pages) AD

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Data Sheet

ADRF5702

APPLICATIONS INFORMATION

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Rev. A | 26 of 27

The ADRF5702 has one power supply pin (VDD) and ten control

pins (PS, LE, and D0 to D7). Figure 56 shows the external com-

ponents and connections for the supply and control pins. The

supply pin (VDD) is decoupled with 100pF multilayer ceramic ca-

pacitor. Place the decoupling capacitor as close as possible to the

ADRF5702. Because the RF lines are biased at a nonzero voltage,

DC blocking capacitors are required. The device pinout allows the

placement of the decoupling capacitors close to the ADRF5702.

Refer to the Pin Configuration and Function Descriptions section for

additional information.

Figure 56. Simplified Application Circuit

RECOMMENDATIONS FOR PCB DESIGN

The RF ports are matched to 50Ω internally, and the pinout is

designed to mate a coplanar waveguide (CPWG) with a 50Ω char-

acteristic impedance on the PCB. Figure 57 shows the referenced

CPWG RF trace design for an RF substrate with 8mil thick Rogers

RO4003 dielectric material. The RF trace with a 14mil width and

a 7mil clearance is recommended for 1.5mil finished copper thick-

ness.

Figure 57. Example PCB Stack-Up

Figure 58 shows the routing of the RF traces, supply, and control

signals from the ADRF5702. The ground planes are connected with

as many filled through vias as allowed for optimal RF and thermal

performance. The primary thermal path for the device is the bottom

side.

Figure 58. PCB Routings

Figure 59 shows the recommended layout from the device RF pins

to the 50Ω CPWG on the referenced stack-up. PCB pads are drawn

1:1 to the device pads. The ground pads are drawn solder mask

defined, and the signal pads are drawn as pad defined. The RF

trace from the PCB pad is extended to the device edge and tapered

to the RF trace with a 45° angle. The paste mask is designed to

match the pad without any aperture reduction. The paste is divided

into multiple openings for the paddle.

Figure 59. Recommended ATTIN Pin and ATTOUT Pin Transitions

For alternate PCB stack-ups with different dielectric thickness and

CPWG design, contact Analog Devices, Inc., Technical Support for

further recommendations.

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