TSC2003IPWR datasheet(18/30 Pages) TI2

18 / 30 page

TSC2003

SBAS162G

www.ti.com

I2C High-Speed Operation

The TSC2003 can operate with high-speed I2C masters. To

do so, the simple resistor pull-up on SCL must be changed

to the active pull-up, as recommended in the I2C specification.

The I2C bus will be operating in standard or fast mode

initially. Following a START condition, the master will send

the code 00001xxx, which the slave will not acknowledge. At

this point, the bus is now operating in high-speed mode. The

bus will remain in high-speed mode until a STOP condition

occurs. Therefore, to maximize throughput only repeated

STARTs should be used to separate transactions.

Since the TSC2003 may not have completed a conversion

before a read to the part can be requested, the TSC2003 is

capable of stretching the clock until the converted data is

stored in its internal shift register. Once the data is latched,

the TSC2003 will release the clock line so that the master

can receive the converted data. A complete high-speed

Conversion Cycle is shown in Figure 14.

Data Format

The TSC2003 output data is in Straight Binary format, as

shown in Figure 15. This shows the ideal output code for the

given input voltage, and does not include the effects of

offset, gain, or noise.

8-Bit Conversion

The TSC2003 provides an 8-bit conversion mode (M = 1)

that can be used when faster throughput is needed, and the

digital result is not as critical (for example, measuring pres-

sure). By switching to the 8-bit mode, a conversion result can

be read by transferring only one data byte.

This shortens each conversion by four bits and reduces data

transfer time which results in fewer clock cycles and provides

lower power consumption.

D11

D10

PD1

PD0

SCLH is stretched LOW until A/D Converter is finished converting data.

F/S Mode

HS-Mode Enabled

A/D Converter Power-Down Mode

A/D Converter Powers Up and Begins Sampling

Fixed Address Part

Programmable

A/D Converter Stops Sampling and Begins Conversion Using Internal Clock

A/D Converter Goes Into Power-Down Mode After Finishing Conversion (If PD0 = 0)

Exit HS-Mode and Enter F/S Mode

16 Bits + Ack

S = START

Sr = REPEATED START

P = STOP

= Master Controls Bus

= Slave Controls Bus

FIGURE 14. High-Speed I2C Mode Conversion Cycle.

FS = Full-Scale Voltage = V

REF

(1)

1LSB = V

REF

(1)/4096

FS – 1LSB

11...111

11...110

11...101

00...010

00...001

00...000

1LSB

NOTES: (1) Reference voltage at converter: +REF – (–REF). See Figure 2.

(2) Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 2

Input Voltage(2) (V)

FIGURE 15. Ideal Input Voltages and Output Codes.

LAYOUT

The following layout suggestions should provide optimum

performance from the TSC2003. However, many portable

applications have conflicting requirements concerning power,

cost, size, and weight. In general, most portable devices

have fairly “clean” power and grounds because most of the

internal components are very low power. This situation would

mean less bypassing for the converter's power, and less

concern regarding grounding. Still, each situation is unique,

and the following suggestions should be reviewed carefully.

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