5.4 Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted).

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE RANGE

VDD

Supply voltage for LVCMOS core logic Supply voltage for LPSDR

low-speed interface (1) (2)

1.71

1.8

1.95

V

VDDI

Supply voltage for SubLVDS receivers (1) (2)

1.71

1.8

1.95

V

VOFFSET

Supply voltage for HVCMOS and micromirror electrode (1) (2) (3)

9.5

10

10.5

V

VBIAS

Supply voltage for mirror electrode (1) (2)

17.5

18

18.5

V

VRESET

Supply voltage for micromirror electrode (1) (2)

–14.5

–14

–13.5

V

| VDDI - VDD |

Supply voltage delta (absolute value) (1) (2) (4)

0.3

V

| VBIAS-VOFFSET |

Supply voltage delta (absolute value) (1) (2) (5)

10.5

V

| VBIAS - VRESET |

Supply voltage delta (absolute value) (1) (2) (6)

33

V

LPSDR INTERFACE

VIH

High-level input voltage

0.7 x VDD

V

VIL

Low-level input voltage

0.3 x VDD

V

VIH(AC)

AC input high voltage

0.8 × VDD

VDD + 0.3

V

VIL(AC)

AC input low voltage

–0.3

0.2 × VDD

V

VHyst

Input Hysteresis

0.1 × VDD

0.4 × VDD

V

fmax_LS

Clock frequency for low speed interface LS_CLK (7)

108

120

130

MHz

DCDIN

LSIF duty cycle distortion (LS_CLK) (7)

44

56

%

SUBLVDS INTERFACE

fmax_HS

Clock frequency for high-speed interface DCLK (8)

600

720

MHz

DCDIN

LVDS duty cycle distortion (DCLK)

48

52

%

| VID |

LVDS differential input voltage magnitude (8)

150

250

350

mV

VCM

Common mode voltage (8)

700

900

1100

mV

VSUBLVDS

SubLVDS voltage (8)

525

1275

mV

ZIN

Internal differential termination resistance

80

100

120

Ω

TEMPERATURE DIODE

ITEMP_DIODE

Max current source into Temperature Diode

120

µA

ENVIRONMENTAL

TARRAY

Array temperature, long-term operation (9) (10) (11)

-40

105

°C

QAP-ILL

Window aperture illumination overfill (12) (13) (14)

80 mW/mm2

ILLUMINATION

ILLUV

Illumination power at wavelengths < 410 nm (9) (15)

10

mW/cm2

(1)

The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also

required.

(2)

All voltage values are concerning the ground pins (VSS).

(3)

VOFFSET supply transients must fall within specified max voltages.

(4)

To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.

(5)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.

(6)

To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit.

(7)

LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(8)

Refer to the SubLVDS timing requirements in Timing Requirements.

(9)

Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination

reduces the device's lifetime.

(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at the test

point (TP1) shown in Figure 6-5 and the package thermal resistance using the Micromirror Array Temperature Calculation.

(11) Long-term is defined as the usable life of the device.

(12) Applies to region defined in Figure 5-1.

(13) The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the

DMD device assembly for normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area

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DLP3944-Q1

SLVSKK1 – DECEMBER 2025

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