CY28400

Rev 1.0, November 21, 2006

Page 2 of 12

Pin Descriptions

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initialize to their default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface cannot be used during system

operation for power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 1.

The block write and block read protocol is outlined in Table 2

while Table 3 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11011100 (DCh).

Pin

Name

Type

Description

2,3

SRCT_IN, SRCC_IN

I,DIF

0.7V differential SRC inputs from the clock synthesizer

6,7,9,10,19,20,22,23

DIFT/C(2:1) & (6:5)

O,DIF

0.7V differential clock outputs

8,21

OE_1, OE_6

I,SE

3.3V LVTTL active LOW input for three-stating differential

outputs (DIFT2 and DIFT5 are unaffected by the assertion of OE

inputs)

17

HIGH_BW#

I,SE

3.3V LVTTL input for selecting PLL bandwidth

16

SRC_STOP#

I,SE

3.3V LVTTL input for SRC_STOP#, active LOW

15

PWRDWN#

I,SE

3.3V LVTTL input for Power Down, active LOW

13

SCLK

I,SE

SMBus slave clock input

14

SDATA

I/O,OC

Open collector SMBus data

26

IREF

I

A precision resistor is attached to this pin to set the differential

output current

12

PLL/BYPASS#

I

3.3V LVTTL input for selecting fan-out or PLL operation

28

VDD_A

3.3V

3.3V power supply for PLL

27

VSS_A

GND

Ground for PLL

4,25

VSS

3.3V

Ground for outputs

1,5,11,18,24

VDD

GND

3.3V power supply for outputs

Table 1. Command Code Definition

Bit

Description

7

0 = Block read or block write operation

1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

1Start

1Start

2:8

Slave address – 7 bits

2:8

Slave address – 7 bits

9

Write = 0

9

Write = 0

10

Acknowledge from slave

10

Acknowledge from slave

11:18

Command Code – 8 bits

'00000000' stands for block operation

11:18

Command Code – 8 bits

'00000000' stands for block operation

19

Acknowledge from slave

19

Acknowledge from slave