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L6260 Datenblatt(PDF) 18 Page - STMicroelectronics |
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L6260 Datenblatt(HTML) 18 Page - STMicroelectronics |
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18 / 30 page ![]() The read cycle is initiated by setting SLOAD low and clocking in a valid read address. Only four bits of address are necessary, if more than four bits are clocked in, the four MSBs will be ignored (i.e. only the first four bits will be used). If a valid address is detected, the rising edge of R/W will load the desired register into the internal se- rial/parallel register ready for clocking out. The data in the serial/parallel register is then serially clocked out on every rising edge of SCLK (LSB is clocked out first). Additional padded bits clocked out will be zero. Note: If SLOAD is set low with R/W high, the cur- rent contents of the internal shift register can be clocked out. This is useful for a ”read back” of the data last written into the required register. D94IN094 tPER A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 SCLK 4 bit address (FIXED) 12 bit data (FIXED) tRWS tSLS SLOAD R/W tRWH tSLH SDIO Figure 5: Serial Write Timing Diagram The write cycle has a fixed address and data length. Four bits of address and 12 bits of data must be clocked in to allow the data to be loaded into the desired register. The write cycle is initi- ated by setting SLOAD and R/W low. Setting R/W low causes the SDIO line to be tri-stated for data input. SLOAD low enables the internal counter to increment on the rising edge of SCLK. The ad- dress and data are clocked into the chip serially on each rising edge of SCLK as shown above. When both the 4 bits of address and the 12 bits of the data have been clocked in, then the ad- dressed register will be written to with the pro- vided data. Setting SLOAD high will clear the in- ternal logic and tri-state the SDIO line. This also provides a way of safely aborting a write by sim- ply forcing SLOAD high. NOTE: SLOAD must be kept low during the entire duration of the 16 write clocks. D94IN095 tPER A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 SCLK INPUT OUTPUT SLOAD R/W tRWS tSLS SDIO tRWD DATA INVALID HiZ tSCKD Figure 6: Serial Read Timing Diagram L6260 18/30 |
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